Cambridge, Cambridgeshire, East Anglia, United Kingdom Hybrid / WFH Options
Langham Recruitment Limited
basis for 6 months. Responsibilities & Experience: Excellent ATPG/MBIST skills are required. Experience building a new flow from scratch. Must be familiar with Synopsys/Cadence/Mentor industry standard toolsets. Previous experience of EDA tool specification/procurement is nice to have Strong ATE bring up and production more »
Employment Type: Contract, Work From Home
Rate: £60 - £80 per hour, Benefits Outside IR35 Hybrid
debug on RTL and Gate Level Netlist Hands-on knowledge in state-of-the-art EDA tools for DFT, design, and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools TCL scripting more »
Linton, England, United Kingdom Hybrid / WFH Options
Langham Recruitment
basis for 6 months. Responsibilities & Experience: Excellent ATPG/MBIST skills are required. Experience building a new flow from scratch. Must be familiar with Synopsys/Cadence/Mentor industry standard toolsets. Previous experience of EDA tool specification/procurement is nice to have Strong ATE bring up and production more »
debug on RTL and Gate Level Netlist Hands-on knowledge in state-of-the-art EDA tools for DFT, design, and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools TCL scripting more »
conductor/Semi-conductor/GPU/SystemVerilog/System Verilog Assertions/Property Specification Language/Cadence/JasperGold/Siemens EDA/Synopsys If you are interested in this Formal Verification Engineer position, please send a CV to ts@eu-recruit.com By applying to this role you understand more »
synthesis, STA, test insertion, MBIST, formality, GDS layout etc Experience in EDA tools for custom IC development like Siemens Questa for simulation and verification, Synopsys DesignCompiler for synthesis and STA, Spyglass for linting, etc. Experience in writing IP design specifications and block level modules Good knowledge of UVM, SVA, VIP more »
