Senior RTL Design Engineer
- Hiring Organisation
- ARM
- Location
- Bristol, Gloucestershire, United Kingdom
- Salary
- £ 70 K
design using System Verilog, Verilog, or VHDLAbility to navigate high-level design trade-offs and articulate the rationale behind those decisionsKnowledge of ASIC (or FPGA) design methodology and IP signoff methods with a deep understanding of timing/area/complexity trade-offs for complex data-path designsExperience with static ...