Strong understanding of FPGA architectures, toolchains (e.g., Xilinx Vivado, Intel Quartus), and hardware description languages (VHDL/Verilog). Experience with high-speed data centre and GPU interfaces (e.g., PCIe, Ethernet, Infiniband, Tofu). Proficiency in debugging and performance profiling for embedded and high-performance systems. Interest or experience with quantum computing, physics or scientific instruments Experience with integrating hardware More ❯
Strong understanding of FPGA architectures, toolchains (e.g., Xilinx Vivado, Intel Quartus), and hardware description languages (VHDL/Verilog). Experience with high-speed data centre and GPU interfaces (e.g., PCIe, Ethernet, Infiniband, Tofu). Proficiency in debugging and performance profiling for embedded and high-performance systems. Interest or experience with quantum computing, physics or scientific instruments Experience with integrating hardware More ❯
Strong understanding of FPGA architectures , toolchains (e.g., Xilinx Vivado, Intel Quartus), and hardware description languages ( VHDL/Verilog ). Experience with high-speed data centre and GPU interfaces (e.g., PCIe, Ethernet, Infiniband). More ❯
Strong understanding of FPGA architectures , toolchains (e.g., Xilinx Vivado, Intel Quartus), and hardware description languages ( VHDL/Verilog ). Experience with high-speed data centre and GPU interfaces (e.g., PCIe, Ethernet, Infiniband). More ❯
City of London, London, United Kingdom Hybrid/Remote Options
Quant Capital
infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra) to co-design tightly coupled platforms Contributing More ❯
infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams (ASIC, software, infra) to co-design tightly coupled platforms Contributing More ❯
