Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools TCL scripting; Python scripting is a plus Bachelor Degree minimum required in Electronics or other related fields JBRP1_UKTJ more »
digital IF equipment. 3. Produce HDL code for VITA-49 or similar network SDR transport protocols. 4. Expert user of Linux. 5. Scripting in TCL designs utilizing IP Cores for rapid development. 6. Build scripting to support continuous integration. 7. Design and development of test benches to prove Verilog code. more »
This position is a unique opportunity to exercise your ASIC design skills on cutting edge designs. The successful ASIC Design Engineer will have the opportunity to join a business who design the key building blocks for market-leading chips that more »
