15 of 15 Remote/Hybrid SystemVerilog Jobs in Scotland

development stage): Hardware requirements, capture and management Concept development for complex functions and systems FPGA design, implementation, and analysis Applying verification techniques usingVHDL or SystemVerilog, with exposure toUVMwhere applicable Production of material for design reviews Development of test planning, integration, and design verification activities Ensuring all firmware designs comply with ...

Depending on your experience, youll bring some, or all, of the following: Experience in design techniques using VHDL Experience in verification techniques using eitherVHDLor SystemVerilog/UVM. Experience in specifying timing and area constraints forefficientFPGA place and route. Ability toanalysesystem level requirements and derive detailedfirmwarerequirements. Degree (BSc, BEng, MEng ...

juniors and shaping FPGA delivery across UK sites. The role requires a degree in Electrical & Electronic Engineering or equivalent, strong FPGA experience (Verilog/SystemVerilog, VHDL), and eligibility for UK SC security clearance. Hybrid working is available in supported locations. #J-18808-Ljbffr ...

discipline) with an extensive proven background in digital CMOS circuit design Implementation of complex digital circuits and sub-systems in RTL using Verilog/SystemVerilog Understanding of digital system-level design, including use of standard bus protocols, bus architecture design and chip-level clock and reset architectures Verification of block ...

success with complex mixed signal IC's.Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysisSystemVerilog - SVA (SystemVerilog Assertions)Testbench design with verification frameworks like UVM/OVM, e, VMMDebugging skills - RTL - Testbench, OOP - Gate level (including SDF)Strong ability to interpret results ...

success with complex mixed signal IC's.Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysisSystemVerilog - SVA (SystemVerilog Assertions)Testbench design with verification frameworks like UVM/OVM, e, VMMDebugging skills - RTL - Testbench, OOP - Gate level (including SDF)Strong ability to interpret results ...

solver. Preferred Skills and Qualifications: Scripting experience with Python, sh/csh, TCL, MakeObject orientated programming (OOP) - Use of OOP design patternsKnowledge of SVA (SystemVerilog Assertions)Metric driven verification - verification planning, requirements extraction - Directed and constrained random verificationFunctional and code coverage analysisPower aware verification (using CPF/UPF)Testbench design ...

systems. You will shape architectures, guide FPGA design, and collaborate with hardware and software teams across UK sites. The role demands strong VHDL/SystemVerilog/Verilog, experience with FPGA SoCs (Versal), and a track record in demanding, mission-critical environments. #J-18808-Ljbffr ...

Bachelor's, Master's or PhD degree in Electrical Engineering (or related discipline) Comprehensive understanding of digital circuit design in RTL using Verilog and SystemVerilog Knowledge and understanding of verification of block-level digital designs Experience and understanding of synthesis and timing analysis of digital circuits Knowledge of design ...

Job Description: Your impact An exciting opportunity has arisen within Leonardo for a Lead Firmware/FPGA Specialist to work within the Surveillance Sector, developing firmware, working on FPGAs, that underpins both our current proven ...

## Firmware/FPGA Engineers - all levelsApplylocations: GB - Edinburgh: GB - Newcastletime type: Full timeposted on: Posted Todayjob requisition id: R0030762**Job Description:**Salary: Engineer: £37,400 to £53,550/Senior: £45, 200 to £61 ...

Job Description: Salary: Engineer: 37,400 to 53,550/Senior: 45, 200 to 61,950/Principal: 53,300 to 71,400/Lead: 59,400 to 84,955Leonardo UK operates a grade-based ...

/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA (SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience ...

engineers to deliver high-quality silicon solutions. ResponsibilitiesDevelop and execute comprehensive verification plans for complex mixed-signal ASIC designs. Create and maintain testbenches using SystemVerilog/UVM.Write and debug test cases to verify functionality, performance, and corner cases. Perform block-level and full-chip verification, including simulation, coverage analysis … degree in Electrical Engineering, Computer Engineering, or related field.10+ years of experience in digital and/or mixed-signal design verification. Strong proficiency in SystemVerilog, UVM, and simulation tools (Synopsys VCS, Cadence Xcelium).Solid understanding of digital design fundamentals, RTL design, and ASIC development flows. Experience with scripting languages (Python ...

decisions, define robust microarchitectures and work closely with Architecture, Verification and Software Engineering teams to deliver high-performance silicon. You'll work on challenging SystemVerilog RTL Design, contribute to SoC Integration, and help deliver complex semiconductor products from concept through to successful tape-out. What You'll Be Doing Designing … high-quality RTL using SystemVerilog Defining microarchitecture for advanced ASIC and SoC designs Supporting large-scale SoC Integration Developing complex digital hardware for next-generation semiconductor devices Collaborating with ASIC Architects, Verification Engineers and Software Engineers Participating in technical design reviews and influencing engineering decisions Supporting projects throughout the complete ...