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4 of 4 Remote SystemVerilog Jobs in Scotland
Edinburgh, Scotland, United Kingdom Hybrid / WFH Options IC Resources
Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA ( SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯
broughton, central scotland, united kingdom Hybrid / WFH Options IC Resources
Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA ( SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯
livingston, central scotland, united kingdom Hybrid / WFH Options IC Resources
Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA ( SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯
dunfermline, north east scotland, united kingdom Hybrid / WFH Options IC Resources
Degree or equivalent in Electronics/Computer Science or other related discipline. Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis SystemVerilog – SVA ( SystemVerilog Assertions) Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills – RTL – Testbench, OOP – Gate level (including SDF) Scripting experience with Ruby, sh/csh More ❯
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