26 to 27 of 27 UVM Jobs in the South East

parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used by industry leading Companies. Experience of working on projects with teams located internationally. Formal … Formal Verification (Jasper Gold or VC_Formal) Practical experience or desire to learn: Translating design requirements into RTL Deriving functional requirements for verification Systemverilog UVM test benches Scripting languages & REST API’s (e.g. Perl/Python/TCL) Team player with good verbal and written communication skills Formal Verification Desirable ...

Digital Verification Engineer with a strong Semiconductor background involving the verification of complex designs (FPGA or ASIC) and with some UVM experience are sought by an exciting new name in the Semiconductor industry. Competitive salary plus Hybrid working, Shares and good benefits. The successful Digital Verification Engineer will work with … Electrical Engineering related discipline. 5+ years experience working within the semiconductor industry ( 10+ for Lead level). Extensive experience of digital verification with some UVM experience. Track record of verifying complex designs (FPGA/ASIC) ideally in high volume applications. Strong Scripting skills. Deep knowledge of simulation tools and debugging ...