6 of 6 RISC-V Jobs in the UK

designs, helping raise verification standards to the highest commercial level. Your work will span block- and system-level verification across designs including OpenTitan , RISC-V cores, cryptographic CPUs (OTBN), crypto accelerators, and peripherals such as USB, I2C, and SPI. Responsibilities Design, implement, and debug SystemVerilog/UVM testbenches ...

with demonstrable reverse engineering experience) Reverse engineering across various architectures and platforms; including x86/64, ARM. Experience with other platforms such as MIPS, RISCV and others are desirable Experience with disassemblers and decompilers (IDA Pro, Binary Ninja, or Ghidra) Knowledge of common exploitation countermeasures and their bypasses ...

have an exciting opportunity in Cambridge for a Principal Verification Engineer to lead verification of open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals . What Youll Do: Lead design, implementation, and debugging of SystemVerilog/UVM testbenches Develop verification plans, tests ...

have an exciting opportunity in Cambridge for a Principal Verification Engineer to lead verification of open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals . What Youll Do: Lead design, implementation, and debugging of SystemVerilog/UVM testbenches Develop verification plans, tests ...

have an exciting opportunity in Cambridge for a Principal Verification Engineer to lead verification of open-source digital designs, including OpenTitan, RISC-V cores, OTBN, crypto accelerators, and peripherals . What Youll Do: Lead design, implementation, and debugging of SystemVerilog/UVM testbenches Develop verification plans, tests … experience through tapeout C and/or Python for test automation Git/GitHub and team collaboration experience Nice to Have: Formal verification, RISC-V/ISA experience, security verification, post-silicon debug ...

designs, helping raise verification standards to the highest commercial level. Your work will span block- and system-level verification across designs including OpenTitan , RISC-V cores, cryptographic CPUs (OTBN), crypto accelerators, and peripherals such as USB, I2C, and SPI. Responsibilities Design, implement, and debug SystemVerilog/UVM testbenches … through tapeout C and/or Python for tests and automation Git/GitHub and collaborative team experience Desirable Formal verification (e.g. Jasper) RISC-V or ISA experience Security verification knowledge Silicon bring-up or post-silicon debug Technical leadership experience ...