6 of 6 Remote/Hybrid RISC-V Jobs in the UK

Further development of proven prototypes to a deployment standard Development of software in a real-time embedded environment using Linux. (e.g. Microblaze or RISC-V using C/C++) Experience of working with and configuring embedded Linux systems with tools such as Buildroot and Yocto Experience of working ...

work with U‐Boot, kernel configuration and device trees. You will engage in real‐time embedded development using platforms such as Microblaze or RISC‐V and work with Linux device drivers, DMA and interrupts. Requirements (Essential) Strong experience as a Software Engineer, programming Embedded Systems using C/ ...

Further development of proven prototypes to a deployment standard Development of software in a real-time embedded environment using Linux. (e.g. Microblaze or RISC-V using C/C++) Experience of working with and configuring embedded Linux systems with tools such as Buildroot and Yocto Experience of working ...

development PCB design exposure (e.g., KiCAD) Prototype assembly and hands-on engineering Project coordination or leadership experience Experience with non-ARM microcontrollers (AVR, RISC-V, ESP-class devices) What’s on Offer Competitive salary package Flexible full-time or part-time arrangements (for experienced engineers) Hybrid working model ...

delivering commercial-grade, tapeout-ready silicon alongside world-class partners. The Role Apply industrial-strength verification across block- and system-level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification plans … Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. ...

delivering commercial-grade, tapeout-ready silicon alongside world-class partners. The Role Apply industrial-strength verification across block- and system-level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). xkybehq Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification … Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. ...