8 of 8 Remote/Hybrid UVM Jobs in the UK

design implementations using VHDL, Simulink, etc., targeting Xilinx, Intel, and Microsemi devices. Ability to verify complex FPGA implementations using VHDL and System Verilog/UVM test-bench methodologies. Proficiency in FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim). Strong skills in generating low-level software (C) for FPGA ...

tape-out, including performance review, analysis, costing, and optimisation Understanding of the product's design & verification needs, standardisation, adherence to frameworks and methodolgies e.g. UVM Excellent communicator, with a keen interest in team collaboration and a clear approach to the design & development process Bonus/"Nice-to-have" skills Digital ...

Digital Verification Engineer with a strong Semiconductor background involving the verification of complex designs (FPGA or ASIC) and with some UVM experience is sought by an exciting new name in the Semiconductor industry. Competitive salary plus Hybrid working and good benefits. Rewarding opportunity for a Digital Verification Engineer seeking ...

parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used by industry leading Companies. Experience of working on projects with teams located internationally. Verification … z2bz0 years of digital ASIC design and verification experience Vast experience of: Translating design requirements into RTL Deriving functional requirements for verification Systemverilog UVM test benches Scripting languages & REST API’s (e.g. Perl/Python/TCL) Team player with good verbal and written communication skills Verification Engineer Desirable skills ...

Digital Verification Engineer with a strong Semiconductor background involving the verification of complex designs (FPGA or ASIC) and with some UVM experience is sought by an exciting new name in the Semiconductor industry. Competitive salary plus Hybrid working and good benefits. Rewarding opportunity for a Digital Verification Engineer seeking … Masters Degree in Electronic/Electrical Engineering related discipline. Proven experience of working within the semiconductor industry. Industrial experience of digital verification with some UVM experience. Track record of verifying complex designs (FPGA/ASIC) ideally in high volume applications. Scripting skills. Good knowledge of simulation tools and debugging techniques. ...

Digital Verification Engineer with a strong Semiconductor background involving the verification of complex designs (FPGA or ASIC) and with some UVM experience is sought by an exciting new name in the Semiconductor industry. Competitive salary plus Hybrid working and good benefits. Rewarding opportunity for a Digital Verification Engineer seeking … Masters Degree in Electronic/Electrical Engineering related discipline. Proven experience of working within the semiconductor industry. Industrial experience of digital verification with some UVM experience. Track record of verifying complex designs (FPGA/ASIC) ideally in high volume applications. Scripting skills. Good knowledge of simulation tools and debugging techniques. ...

system-level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification plans, tests, and coverage Review contributions and resolve regressions Support CI/test infrastructure Collaborate with partners through tapeout Requirements 5+ years … industry verification experience Strong SystemVerilog and UVM Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. ...

level designs including RISC-V cores, cryptographic IP (OTBN), and key peripherals (USB, I2C, SPI). xkybehq Key Responsibilities Develop and debug SystemVerilog/UVM testbenches Create verification plans, tests, and coverage Review contributions and resolve regressions Support CI/test infrastructure Collaborate with partners through tapeout Requirements 5+ years … industry verification experience Strong SystemVerilog and UVM Full verification lifecycle experience through tapeout C and/or Python for automation Git/GitHub collaboration Desirable: Formal verification (Jasper), RISC-V/ISA knowledge, security verification, silicon bring-up, or technical leadership experience. ...