26 to 50 of 54 Perl Jobs in the UK excluding London

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Exeter, Devon, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Bedford, Bedfordshire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Colchester, Essex, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Norwich, Norfolk, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Portsmouth, Hampshire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Reading, Berkshire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
East Anglia, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Lincoln, Lincolnshire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Cheltenham, Gloucestershire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Newcastle upon Tyne, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
North East, Glasgow, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
York, North Yorkshire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Hull, East Yorkshire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Milton Keynes, Buckinghamshire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Bradford, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Newport, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Edinburgh, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Maidstone, Kent, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Northampton, Northamptonshire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Oxford, Oxfordshire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Chesterfield, Derbyshire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Hemel Hempstead, Hertfordshire, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
Crawley, West Sussex, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Senior Silicon Design Engineer

Hiring Organisation
Advanced Micro Devices
Location
West Bromwich, West Midlands, UK
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

Staff RTL/Digital Design Engineer - (CPU Team) - Visas Transfers Supported

Hiring Organisation
European Tech Recruit
Location
Cambridge, England, United Kingdom
power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information ...