5 of 5 SystemVerilog Jobs in Wales

tests and scripts Required profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl ...

verification team Proven track record in simulation-based verification for ASIC or FPGA blocks and subsystems. Strong experience in UVM-based verification in SystemVerilog, with a deep understanding of the framework. Experience of verification coverage closure in an ASIC or FPGA project. Strong problem-solving skills. Experience of Synopsys functional ...

verification team Proven track record in simulation-based verification for ASIC or FPGA blocks and subsystems. Strong experience in UVM-based verification in SystemVerilog, with a deep understanding of the framework. Experience of verification coverage closure in an ASIC or FPGA project. Strong problem-solving skills. Experience of Synopsys functional ...

Job Title: FPGA Engineer Location: Bristol - Hybrid 3+ days on-site per week Role Type: Contract Duration : 12 months Rate: £60.00 - £80.00 per hour - Inside IR35 Our client, an established engineering consultancy, require an experienced ...

trust What You’ll Be Doing Define digital architectures for AI accelerators, data paths, and SoC subsystems Develop high-quality, synthesizable RTL (Verilog/SystemVerilog). Run synthesis, STA, and DFT using industry-standard digital design tools Lead design reviews and help establish best practices and design flows Support tapeout ...