west london, south east england, United Kingdom Hybrid / WFH Options
Logik Source
considerations in hardware design. Experience using PCIe, CXL, RDMA, DDR4, bare metal use of high-speed transceivers, Ethernet, IP. Excellent skills in SystemVerilog/Verilog/VHDL. The company offer an excellent salary, along with a bonus up to 85%, flexible and hybrid working, exciting technology and a great team More ❯
south west london, south east england, United Kingdom Hybrid / WFH Options
Logik Source
considerations in hardware design. Experience using PCIe, CXL, RDMA, DDR4, bare metal use of high-speed transceivers, Ethernet, IP. Excellent skills in SystemVerilog/Verilog/VHDL. The company offer an excellent salary, along with a bonus up to 85%, flexible and hybrid working, exciting technology and a great team More ❯
south west london, south east england, United Kingdom Hybrid / WFH Options
Octagon Group
high-throughput applications. What skills and experience is required: FPGA Design, development and testing experience Previous experience in using SystemVerilog, VHDL and/or Verilog Software skills using C/C++ or Python Exposure to Quartus and/or Vivado Any exposure or understanding of low latency, machine learning, or More ❯
west london, south east england, United Kingdom Hybrid / WFH Options
Octagon Group
high-throughput applications. What skills and experience is required: FPGA Design, development and testing experience Previous experience in using SystemVerilog, VHDL and/or Verilog Software skills using C/C++ or Python Exposure to Quartus and/or Vivado Any exposure or understanding of low latency, machine learning, or More ❯
TW1, St. Margarets and North Twickenham, Greater London, United Kingdom Hybrid / WFH Options
Platform Recruitment
Design, develop and test analogue and digital electronics. + Manage QA, including documentation, reviews, validation, change and configuration management + Programming with VHDL/Verilog code for FPGAs Skills Needed: + Degree within Electronics or related field + Strong understanding around analogue and digital circuit design + Experience with DSP More ❯
Stacks: SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC, RTL RDC Verilog/System Verilog (VHDL OR Verilog) RTL Design: Good technical leadership skills with ability to guide the CWFs on SoC execution Should have a good understanding of SoC architecture and should be able to map More ❯
south west london, south east england, United Kingdom
ALOIS Solutions
Stacks: SoC Integrtion, IP integration RTL design & Coding RTL lint, RTL CDC, RTL RDC Verilog/System Verilog (VHDL OR Verilog) RTL Design: Good technical leadership skills with ability to guide the CWFs on SoC execution Should have a good understanding of SoC architecture and should be able to map More ❯
south west london, south east england, United Kingdom
ALOIS Solutions
show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases More ❯
show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases More ❯
south west london, south east england, United Kingdom
IC Resources
verification. Must have expertise in some of the following domains: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets. Expertise in Verilog/System Verilog for coding and verification. Proficiency in RTL design techniques. Experience in using UVM for functional verification of ASIC designs. Experience with FPGA More ❯
verification. Must have expertise in some of the following domains: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets. Expertise in Verilog/System Verilog for coding and verification. Proficiency in RTL design techniques. Experience in using UVM for functional verification of ASIC designs. Experience with FPGA More ❯