2 of 2 Verilog Jobs in Wolverhampton

logical equivalency checking (LEC) · Verification debug support · Lint checks – RTL, CDC, RDC, DFT, UPF Required Skills & Knowledge: · Micro-architecture design, RTL coding in System Verilog for either of below blocks: o Power management control o Subsystem/SOC reset control o Subsystem/SOC clock control o Subsystem/SOC More ❯

show all implemented tests passing on the RTL. • Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases More ❯