Senior Physical Design Engineer
Farnborough, Hampshire, South East, United Kingdom
Hays
implementation at block and chip level Insertion of DFT test structures and chip level integration, capture, and simulation Skills needed to succeed COT/ASIC physical design flow covering: Synthesis, Floor planning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) and Timing Closure more »
Employment Type: Permanent
Salary: £80,000
Posted: