flow Design and development of new profiling tools and methodologies The creation of automated tests, contributing to our DevOps pipeline to maintain the fast cadence and high quality of our releases High quality engineering through approach reviews, code reviews and following modern agile software development process Mentoring and coaching more »
ideally, some grounding in assembly language (ideally Arm assembler) and object-orientated coding (e.g. C++) Skilled in simulation Tools: Verdi/VCS, QuestaSim and Cadence tools. Confident user of a UNIX environment and shell programming/scripting in e.g. Makefile, Python, Tcl, sh, bash. Comprehension and use of data more »
Experience Design and development of new profiling tools and methodologies The creation of automated tests, contributing to our DevOps pipeline to maintain the fast cadence and high quality of our releases High quality engineering through approach reviews, code reviews and following modern agile software development process. REQUIRED SKILLS AND more »
delivery. You will have an excellent understanding of modern transceiver architectures and a good working knowledge of RF IC layout optimisation. Experience with the Cadence Analog Design environment is essential and experience with advanced circuit simulation tools and EM simulation tools is ideal. Desirable skills include: Excellent knowledge of more »
Cambridge, England, United Kingdom Hybrid / WFH Options
WeDo
How do you take a team to your level of quality standards? How do you use automation to increase the speed of the delivery cadence (currently 4 times a year, with a clear objective of getting this to every 3 weeks) As a Lead QA Engineer, you will have more »
following areas would enhance the application: A broad knowledge of EDA tools for schematic entry PCB layout and signal integrity analysis Experience in using Cadence CIS, Mentor PADs Layout, Allegro PCB design suite and Hyperlynx tools Embedded software knowledge to test and debug the design with a creative and more »
Power Management (PMIC), designing amplifiers and bandgap references is required. Experience in Analog IC Design and verification techniques is essential as well as strong Cadence and Mentor tools knowledge. You will need the ability to coordinate with different groups and be able to define the requirements so excellent written more »
Power Management (PMIC), designing amplifiers and bandgap references is required. Experience in Analog IC Design and verification techniques is essential as well as strong Cadence and Mentor tools knowledge. You will need the ability to coordinate with different groups and be able to define the requirements so excellent written more »
to write coherent documentation. Desirable Experience: A broad knowledge of EDA tools for schematic entry PCB layout and signal integrity analysis. Experience in using Cadence CIS, Mentor PADs Layout, Allegro PCB design suite and Hyperlynx tools. Embedded software knowledge to test and debug the design with a creative and more »
Cambridge, Cambridgeshire, East Anglia, United Kingdom
La Fosse Associates Ltd
following areas would enhance the application: A broad knowledge of EDA tools for schematic entry PCB layout and signal integrity analysis Experience in using Cadence CIS, Mentor PADs Layout, Allegro PCB design suite and Hyperlynx tools Embedded software knowledge to test and debug the design with a creative and more »
following areas would enhance the application: • A broad knowledge of EDA tools for schematic entry PCB layout and signal integrity analysis • Experience in using Cadence CIS, Mentor PADs Layout, Allegro PCB design suite and Hyperlynx tools • Embedded software knowledge to test and debug the design with a creative and more »
schedules Organise/plan and direct block work in remote sites Practical hands-on experience in all aspects of layout design, verification and debug Cadence layout-(G)XL and Caliber proficiency Experience in floor planning and routing strategies Experience of electrically aware design including EM/IR/ESD more »
on experience) What you need to be successful in this role: Experience writing Hardware description languages ideally SystemVerilog Experience using EDA simulators (Siemens, Synopsys, Cadence) Experience working with version control and code review systems (Git, Gerrit) Experience with CI (Jenkins) Scripting for design automation (Python, Perl, JSON, Tcl, Make more »
Cambridge, England, United Kingdom Hybrid / WFH Options
IC Resources
offered with this role. Required skills for the Principal Semiconductor Packaging Engineer will include: Strong IC semiconductor packaging experience and knowledge Advanced packaging knowledge Cadence EDA tool experience SI/EMC analysis experience Strong communication skills and a start-up mentality Degree qualified Please contact Rachel Anderson for further more »
Cambridge, England, United Kingdom Hybrid / WFH Options
Platform Recruitment
Strong experience with modelling and verification for ASIC implementation. Experience with SystemVerilog and Verilog-A. EDA tool experience for custom analogue IC development like Cadence, Mentor Graphics. more »
correct operation and compliance with target performance specifications Qualifications: Deep knowledge on Bipolar (BJT) and CMOS Integrated circuit design with BiCMOS processes Expertise in Cadence IC design tool flows and test bench design Demonstrated capabilities for Circuit analysis and delivery of design solutions Excellent team player with strong communication more »
in full ASIC design using mixed BJT and CMOS technologies. Requirements : Demonstrated capabilities for Circuit analysis and delivery of design solutions Expert knowledge of Cadence tool workflow for schematic capture, simulation and layout In-depth experience in the design of bandgaps, LDOs, and Opamps Experience in developing high-performance more »
more years of experience in package drawing Able to choose trade-offs to obtain best drawing strategy Proficient in usage of package drawing tools (Cadence APD/Allegro or equivalent) “NICE TO HAVE” SKILLS AND EXPERIENCE : Good understanding SoC implementations and data exchanged between SoC team and package designmore »
/RF circuits in deep sub-micron technology as well as a strong analytical approach with a clear track record of success and delivery • Cadence Virtuoso Design Framework Experience • Ability to work and interact with engineering teams across multiple disciplines during ASIC project stream development • Great communication skills and … RF PA • Understanding of Radio systems, gain and noise budgeting, phase noise and intermodulation mechanisms • Experience on ESD design and strategy overview • Experience on Cadence/Calibre verification tools • Experience on revision control tools more »
Key Requirements: Strong experience in architecting/implementing formal verification environments. Experience in SVA and PSL. Experience working with industry-leading formal tools. eg. Cadence, Jasper Gold, Siemens EDA QuestaFormal, or Synopsys. Keywords: Formal Verification/Semiconductor/Semi conductor/Semi-conductor/GPU/SystemVerilog/System … Verilog Assertions/Property Specification Language/Cadence/JasperGold/Siemens EDA/Synopsys If you are interested in this Formal Verification Engineer position, please send a CV to ts@eu-recruit.com By applying to this role you understand that we may collect your personal data and store more »
DDR), and PCB stack-ups and topologies. These will make your profile stand out: Proficient in industry-standard EDA tools for schematic capture (e.g., Cadence CIS, Mentor PADs Layout), PCB layout (e.g., Allegro PCB Designer), and signal integrity analysis (e.g., Hyperlynx). Combine hardware expertise with embedded software knowledge … C++). Interested? Apply directly through LinkedIn, or send your CV to george@eu-recruit.com Keywords: PCB/Board Design/Board Designer/Cadence CIS/PADs/Allegro/DDR/LSI/PCIe/Printed Circuit Board/Verilog/VHDL/Cambridge/UK By more »
