2 Permanent Senior Verification Engineer Jobs in Cambridge

Senior Verification Engineer (UVM) We are working with a world-leading technology company who are looking to grow their team in Cambridge, UK with experienced Verification Engineers. This will be a full-time permanent position, offering above market compensation, and where required we can provide relocation … and visa support. You will play a key role in developing hardware verification testbenches for next-gen hardware IP. In particular, we are looking for individuals with experience of complex IP/module level designs. The successful candidate should demonstrate the following: Strong knowledge of hardware verification languages … SystemVerilog) along with assembly, C/C++ and scripting. Experience in various verification methodologies, ideally UVM. Exposure to all stages of verification including requirements collection, test plans, testbench implementation, test case development etc. Experience with complex IP/block/module level designs. Fluency in English. more »

FPGA/Embedded System Engineer We think you'll love this opportunity, even if we are slightly biased! As an experienced Design & Verification Engineer Engineer, you will be part of the hardware platform team that builds development platforms for leading CPU and System IP products, that … ability to apply your RTL design skills using SystemVerilog for FPGA and/or ASIC, together with an understanding of FPGA device architecture. For verification you will be using System-Verilog and possibly UVM, this will include coding System Verilog Assertions (SVA) checks, cover-properties, SV coverage groups etc. … Tcl, Make, bash etc will also be required.. Required Skills and Experience: Proven experience of delivering RTL designs in a SoC or FPGA. RTL Verification at both unit and system level, using SV including SVA. Experience of ASIC or FPGA synthesis tools. Unix/Linux skills including shell programming more »