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material for design reviews. - Development of test planning, integration and design verification. - Ensure that all firmware designs follow the company firmware process. - Experience using FPGA technologies from either Xilinx, Intel (Altera) or Microsemi (Actel) and their tools. - Degree (BSc, BEng, MEng, MSc, PhD, EngD) in Electrical & Electronic Engineering (preferable) or related science (e.g. Physics). SC clearance is essential More ❯

detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback Experience with Programmable Logic EDA tools, such as AMD/Xilinx ISE/Vivado, Intel/Altera Quartus, Siemens/Mentor Graphics, Synopsys Synplify, SoftCore Micro embedments in MicroChip, etc. Proven track record to design and implement FPGA modules using Verilog and/or More ❯

detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback • Experience with Programmable Logic EDA tools, such as AMD/Xilinx ISE/Vivado, Intel/Altera Quartus, Siemens/Mentor Graphics, Synopsys Synplify, SoftCore Micro embedments in MicroChip, etc. • Proven track record to design and implement FPGA/ASIC modules using Verilog and More ❯

for designing a comprehensive technical solution that addresses all customer and mission requirements. This includes: Requirements Analysis: Conduct a detailed analysis of past and current government documentation, open-source intel, customer intel, market intel, and competitive intel to understand the client's needs and technical requirements. Validate the requirements and develop questions/suggestions for follow More ❯

co-design and debugging tools (Oscilloscope, JTAG, Signal Analyzer). • Ability to work in a fast-paced environment and manage multiple projects effectively. Preferred Qualifications: • Experience with Xilinx, Altera (Intel FPGA), or Lattice FPGA architectures. • Knowledge of C/C++, Python for FPGA development. • Understanding of high-performance computing, signal processing, and networking applications. • Familiarity with System Verilog, UVM More ❯

design/debug with Ethernet, TCP/IP protocols. Our company has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS). This is More ❯

digital design with VHDL and/or Verilog/SystemVerilog Proven track record performing synthesis, timing closure, and static timing analysis Experience with FPGA tool flows (e.g. Xilinx Vivado, Intel/Altera tools, or similar) Familiarity with simulation/verification tools (ModelSim, Questa, VCS, etc.) Experience working with high-speed interfaces (e.g. multi-gigabit serializers, DDR, memory, LVDS, SERDES More ❯

SVA) • Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet) • Deployed state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), Catapult (HLS). The ideal candidate will have: • Bachelor of Science in Electrical Engineering More ❯

SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux. • Deployed state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), Catapult (HLS). VHDL Experience • Proficient in VHDL >5 yrs, Xilinx FPGA design EDA More ❯

updates. Essential Skills & Experience: Hands-on FPGA design experience with VHDL or Verilog. Proficiency with development environments such as Quartus Prime Pro, ModelSim, Vivado, or ISE. Familiarity with Xilinx, Intel (Altera), and Microsemi (Actel) toolchains. Solid knowledge of version control systems and configuration management practices. Independent verification expertise and technical risk mitigation. Experience with high-speed serial interfaces and More ❯

complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model driven engineering using Matlab and Simulink tools Derivation More ❯

complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model driven engineering using Matlab and Simulink tools Derivation More ❯

complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model driven engineering using Matlab and Simulink tools Derivation More ❯

complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. Auto-generated code using model driven engineering using Matlab and Simulink tools Derivation More ❯

including Mentor EDA: Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus). We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability More ❯

years of RTL design and verification using VHDL, Verilog, or SystemVerilog (willingness to adopt SystemVerilog). 7+ years of RTL synthesis using tools such as Xilinx ISE/Vivado, Intel Quartus, or Microsemi Libero. 7+ years of RTL verification using simulation tools such as Xilinx XSim, QuestaSim/ModelSim, Synopsys VCS, or Cadence NCsim. Active Secret or Top Secret More ❯

years of RTL design and verification using VHDL, Verilog, or SystemVerilog (willingness to adopt SystemVerilog). 5+ years of RTL synthesis using tools such as Xilinx ISE/Vivado, Intel Quartus, or Microsemi Libero. 5+ years of RTL verification using simulation tools such as Xilinx XSim, QuestaSim/ModelSim, Synopsys VCS, or Cadence NCsim. Active Secret or Top Secret More ❯

related field. 5+ years of professional experience in software development, with a focus on C++ and/or Rust . Strong understanding of FPGA architectures , toolchains (e.g., Xilinx Vivado, Intel Quartus), and hardware description languages ( VHDL/Verilog ). Experience with high-speed data centre and GPU interfaces (e.g., PCIe, Ethernet, Infiniband). More ❯

tech roadmap initiatives Essential Requirements of the FPGA Engineer: Solid understanding of FPGA-hardware integration Strong VHDL design & verification skills Hands-on debug & integration in hardware Skilled with Xilinx, Intel (Altera), or Microchip toolsets Desirable Requirements of the FPGA Engineer: Experience with Embedded Firmware (C/C++/Assembler) Knowledge of PCIe/NVMe implementation Understanding of secure design More ❯

including Mentor EDA: Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus). We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability More ❯

or a related field. At least 3+ years of commercial FPGA and general hardware design experience. Proficient in FPGA design using VHDL/SystemVerilog with AMD (Xilinx), Lattice, or Intel (Altera) products. Familiar with high-speed interfaces and advanced simulation methods. Strong communication skills for effective collaboration with team members and clients.What we offer in return Competitive salary, dependent More ❯

or a related field. At least 3+ years of commercial FPGA and general hardware design experience. Proficient in FPGA design using VHDL/SystemVerilog with AMD (Xilinx), Lattice, or Intel (Altera) products. Familiar with high-speed interfaces and advanced simulation methods. Strong communication skills for effective collaboration with team members and clients. What we offer in return Competitive salary More ❯

including Mentor EDA: Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus). We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability More ❯

operations of embedded processors, FPGAs, or SOCs. • Ability to work effectively in a cross-functional team environment. • Familiarity with commercial-grade components such as Xilinx Virtex, Microsemi SmartFusion, or Intel Stratix is desirable. • Active security clearance is strongly preferred. Candidates without an active clearance must be able to obtain a secret clearance upon starting this position. • Candidates must be More ❯

with FPGA Integrated Design Environment tool sets such as Xilinx Vivado and Mentor Graphics ModelSim. • Experience with latest System on a Chip (SoC) implementations such as Xilinx Zynq Ultrascale+, Intel Stratix-10, and Xilinx RFSoC. • Proficiency in hardware descriptor languages, HDL (VHDL, Verilog) and/or MATLAB model(s). • Ability to perform design constraints generation and verification as More ❯