Senior Physical Layout Engineer
South East London, England, United Kingdom
Flux Computing
micro‐bump/flip‐chip escape routing so 100 + channels meet skew and return‐loss targets. Perform parasitic extraction and EM/IR, thermal and electro‐migration analysis (Cadence Quantus/Calibre xRC, Voltus, EMX/HFSS), iterate with circuit designers to close speed, noise and phase‐noise margins. Optimise critical paths for minimal capacitance and series inductance … production CMOS technologies, with multiple tape‐outs that include > 10 GHz analog front‐ends or 56 ‐ 112 Gb/s SerDes/CDR/PLL blocks. Expert user of Cadence Virtuoso custom layout tools plus sign‐off flows (PVS/Calibre DRC‐LVS, Quantus/StarRC, Voltus/RedHawk). Deep understanding of parasitic‐aware matching, device symmetry, shielding More ❯
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