1 of 1 Design for Test Jobs in Central London

authority for every digital block that underpins our OTPU. Responsibilities Architect, plan and deliver the digital top level of a multi‐lane optical compute ASIC—RTL, synthesis, DFT/DFD, static‐timing and physical implementation. Lead cross‐functional teams (digital, analog, verification, layout, packaging, test, firmware) through all silicon lifecycle stages: architecture ► spec ► RTL ► physical design … steering DACs, high‐speed SerDes, PLLs and clock‐mesh networks to guarantee end‐to‐end timing determinism and low‐latency control loops. Drive design verification strategy —UVM test‐benches, gate‐level sims, FPGA prototyping—and own silicon bring‐up test plans that hit first‐silicon functional goals. Optimise multi‐lane protocols for bandwidth scaling … sensors, SerDes, RF SoCs, etc.). Strong command of RTL design (SystemVerilog/Verilog), CDC/RDC, STA, place‐and‐route, power intent (UPF/CPF) and DFT/DFD methodologies. Demonstrated success coordinating multi‐lane data paths, clock distribution and fast‐settling DAC/ADC control loops while closing timing and power at advanced nodes. Solid understanding More ❯