Join to apply for the IC Physical Design Engineer role at Fractile Join to apply for the IC Physical Design Engineer role at Fractile Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking … the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future … addressing IR drop, electromigration, and low-power design techniques. Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance. Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation. Utilise EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Graphics Calibre, and More ❯
London, England, United Kingdom Hybrid / WFH Options
microTECH Global LTD
Join to apply for the Digital Design & Verification Engineer – Graduate/Junior role at microTECH Global LTD Join to apply for the Digital Design & Verification Engineer – Graduate/Junior role at microTECH Global LTD Job Title: Digital Design & Verification Engineer – Graduate/Junior Position: Graduates & Junior Location: Hertfordshire Hybrid Salary … Range: Negotiable Client Information We are building a revolutionary RISC-V-based GPU and AI platform, and we’re hiring talented engineers in Hardware Design and Hardware Verification to join us on this mission. If you thrive on innovation and want to work on cutting-edge vector processing and neural compute technologies, this is your opportunity. Job Description … Familiarity with RISC-V ISA is a plus, not a must Understanding of pipelining, memory hierarchies, or parallel compute concepts Interest in learning physical design fundamentals (timing, DFT, floorplanning) Experience using EDA tools (e.g., Synopsys, Cadence, or similar) during academic or internship projects Scripting knowledge in Python, TCL, or equivalent languages BS or MS in Electrical Engineering, Computer More ❯
Associate Applications Engineer IC (w/m/d) - Graduate Program Join to apply for the Associate Applications Engineer IC (w/m/d) - Graduate Program role at Siemens EDA (Siemens Digital Industries Software) Associate Applications Engineer IC (w/m/d) - Graduate Program Join to apply for the Associate Applications Engineer IC (w … Siemens Digital Industries Software) Discover your career with us at Siemens Digital Industries Software! We are a leading global software company dedicated to the world of computer-aided design, 3D modeling, and simulation— helping innovative global manufacturers design better products, faster! With the resources of a large company, and the energy of a software start-up … customers can achieve their full potential. We at Siemens DISW develop sophisticated software tools that span the full breadth of semiconductor and electrical systems solutions, including integrated circuit design and verification, PCB design and manufacturing solutions, cable harness tools, and embedded software. As an Associate Application Engineer m/f/d , you will be involved More ❯
Hardware Design Engineer, Amazon Ring Vietnam Design Center Job ID: 2794277 | Amazon Corporate Services Vietnam Company Limited Ring is a leader in developing security products, such as Video Doorbells, Spotlights and Cameras. Our hardware team aims to develop reliable and robust products that delight our customers. Ring is seeking a Hardware Design Engineer who … as hands-on design work to create the next generation of Ring products. You’ll also help identify design risks, propose improvements, and even guide test coverage strategy. When you look at the test results, you can figure out what we can do better. About the team We’re a friendly team, always eager … recommendation fordesign teams. * Proficiency in hardware design software such as Altium 365, Cadence, or similar eCAD tools. * Proficiency in creating and executing test plans for hardware components and technical document skills. * Hands-on experience in the lab environments with test equipment such as oscilloscope, multi-meter, etc. * Strong problem More ❯
Job Title: Senior Digital Design Engineer Position: Full time permanent position Location: Bristol Salary Range: 50K – 80K GBP per annum depending on experience Client Information: My client is looking to strengthen their ASIC Digital Design team. Looking for bright candidates who have an enthusiasm and aptitude for working with ASIC chips. Designing … chips for customers ranging from start-ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. You will have a strong academic record, around 7-10 years’ experience in industry working on ASIC developments and IP design. If you have at least one successful project as Technical Lead, a more senior position could … understanding of all aspects of ASIC FE design, from specification to RTL, and with a basic understanding of RTL to tape out flow ASIC implementation skills (synthesis, DFT, timing closure) Experience to lead one complex IP design and/or full ASIC design, from specification to full RTL Specific expertise in the following technical More ❯
pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We're backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford Sciences Innovations, INKEF Capital and Octopus Ventures, and we … theoreticians and software engineers to create a unique, world-leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology. … providing feedback on the validity of the working principles of a circuit without the assistance of simulation software. Understanding of RF testing and demonstrated experience in the application of DFT of RF blocks. Knowledge of one or more industry-standard EM simulation toolset (ADS, EMX, CDT, HFSS) Strong analytical and problem-solving skills with a high-level of self-management More ❯
Join to apply for the Staff RF IC Design Engineer role at Quantum Motion 1 week ago Be among the first 25 applicants Join to apply for the Staff RF IC Design Engineer role at Quantum Motion Get AI-powered advice on this job and more exclusive features. About The Role And … pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors including Bosch Ventures, Porsche SE, Sony Innovation Fund, Oxford Sciences Innovations, INKEF Capital and Octopus Ventures, and we … providing feedback on the validity of the working principles of a circuit without the assistance of simulation software. Understanding of RF testing and demonstrated experience in the application of DFT of RF blocks. Knowledge of one or more industry-standard EM simulation toolset (ADS, EMX, CDT, HFSS) Strong analytical and problem-solving skills with a high-level of self-management More ❯
Join us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We’re searching for a Digital Design Engineer who is passionate about building and verifying complex, high‐performance ASICs . You will own the definition and execution of verification strategies for … GLS with SDF, and power‐aware checks; work with physical‐design teams on ECOs. Enable post‐silicon bring‐up by generating test vectors, configuring scan/DFT hooks, and supporting FPGA/emulation platforms for firmware and software teams. Mentor junior engineers on verification methodology, code reviews, and best practices; champion continuous‐integration flows, regressions … with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and power‐domain management, DFT/scan and low‐power (UPF/CPF) methodologies. Strong scripting (Python, Tcl, shell) to automate regressions and data analysis. Proven debug skills across RTL, gate‐level and emulation environments. More ❯
Job Title: Hardware Design and Verification Engineer Position: Junior - Mid level Engineers Type: Contract or Permanent Location: Hertfordshire Hybrid Salary Range: Negotiable Client Information: We are building a revolutionary RISC-V-based GPU and AI platform, and we're hiring talented engineers in Hardware Design and Hardware Verification to join us on this mission. If you … thrive on innovation and want to work on cutting-edge vector processing and neural compute technologies, this is your opportunity. Design Responsibilities: Architect and implement RTL for critical blocks within our RISC-V vector core GPU Design high-performance, power-efficient compute units for graphics and AI workloads Optimize microarchitecture to meet … accelerator design Familiarity with RISC-V instruction set architecture (preferred) Understanding of graphics pipelines and/or neural network accelerators Awareness of physical design implications (DFT, timing, floorplanning) Proficiency with EDA tools (Synopsys, Cadence, Mentor, etc.) Strong scripting skills in Python, TCL, or similar BS/MS in Electrical Engineering, Computer Engineering, or related field Verification More ❯
solutions through innovation with uncompromising agility. JOB DESCRIPTION: We commit to build upon the drivers and the productivity tools and enhancement of portfolios and software that supports requirements throughout test workflows. With bigger test coverages and taking measurements, automate the test caveats and collaborate with government agencies as they change their laws and regulations and make designs … to be more secure for the pre-build test executives. A team of seven - Time to market pressure is everything: Areas to cover will include validation and production test systems, take measurements and automate the world around you and expand the capabilities, auto sequencing and parallel testing, electromechanical validation, viewing the data, graphical control coding, software … test automation, multiple test vectors, manage & control complex automation sequences. Our perceive approach is to build out a suite of software architecture with predefined functionalities, software defined instruments and tools that work together across all the ground control engineers' workflows. From the planning, to the configuration, the building of the systems, deploying of the systems, managing the systems More ❯
Join us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We’re searching for a Digital Design Engineer who is passionate about building and verifying complex, high‐performance ASICs . You will own the definition and execution of verification strategies for … GLS with SDF, and power‐aware checks; work with physical‐design teams on ECOs. Enable post‐silicon bring‐up by generating test vectors, configuring scan/DFT hooks, and supporting FPGA/emulation platforms for firmware and software teams. Mentor junior engineers on verification methodology, code reviews, and best practices; champion continuous‐integration flows, regressions … with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and power‐domain management, DFT/scan and low‐power (UPF/CPF) methodologies. Strong scripting (Python, Tcl, shell) to automate regressions and data analysis. Proven debug skills across RTL, gate‐level and emulation environments. More ❯
Join us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We’re searching for a Digital Design Engineer who is passionate about building and verifying complex, high‐performance ASICs . You will own the definition and execution of verification strategies for … GLS with SDF, and power‐aware checks; work with physical‐design teams on ECOs. Enable post‐silicon bring‐up by generating test vectors, configuring scan/DFT hooks, and supporting FPGA/emulation platforms for firmware and software teams. Mentor junior engineers on verification methodology, code reviews, and best practices; champion continuous‐integration flows, regressions … with at least two tape‐outs. Mastery of SystemVerilog/UVM, functional coverage, constraint‐random stimulus and scoreboards. Deep understanding of clock‐domain crossing, reset and power‐domain management, DFT/scan and low‐power (UPF/CPF) methodologies. Strong scripting (Python, Tcl, shell) to automate regressions and data analysis. Proven debug skills across RTL, gate‐level and emulation environments. More ❯
authority for every digital block that underpins our OTPU. Responsibilities Architect, plan and deliver the digital top level of a multi‐lane optical compute ASIC—RTL, synthesis, DFT/DFD, static‐timing and physical implementation. Lead cross‐functional teams (digital, analog, verification, layout, packaging, test, firmware) through all silicon lifecycle stages: architecture ► spec ► RTL ► physical design … steering DACs, high‐speed SerDes, PLLs and clock‐mesh networks to guarantee end‐to‐end timing determinism and low‐latency control loops. Drive design verification strategy —UVM test‐benches, gate‐level sims, FPGA prototyping—and own silicon bring‐up test plans that hit first‐silicon functional goals. Optimise multi‐lane protocols for bandwidth scaling … sensors, SerDes, RF SoCs, etc.). Strong command of RTL design (SystemVerilog/Verilog), CDC/RDC, STA, place‐and‐route, power intent (UPF/CPF) and DFT/DFD methodologies. Demonstrated success coordinating multi‐lane data paths, clock distribution and fast‐settling DAC/ADC control loops while closing timing and power at advanced nodes. Solid understanding More ❯
authority for every digital block that underpins our OTPU. Responsibilities Architect, plan and deliver the digital top level of a multi‐lane optical compute ASIC—RTL, synthesis, DFT/DFD, static‐timing and physical implementation. Lead cross‐functional teams (digital, analog, verification, layout, packaging, test, firmware) through all silicon lifecycle stages: architecture ► spec ► RTL ► physical design … steering DACs, high‐speed SerDes, PLLs and clock‐mesh networks to guarantee end‐to‐end timing determinism and low‐latency control loops. Drive design verification strategy —UVM test‐benches, gate‐level sims, FPGA prototyping—and own silicon bring‐up test plans that hit first‐silicon functional goals. Optimise multi‐lane protocols for bandwidth scaling … sensors, SerDes, RF SoCs, etc.). Strong command of RTL design (SystemVerilog/Verilog), CDC/RDC, STA, place‐and‐route, power intent (UPF/CPF) and DFT/DFD methodologies. Demonstrated success coordinating multi‐lane data paths, clock distribution and fast‐settling DAC/ADC control loops while closing timing and power at advanced nodes. Solid understanding More ❯
up tasks from start to completion with minimal help. QAEs would be responsible for understanding the domain and the product in detail and coming up with the test strategy/planning, coming up with the test cases, driving the test case sign-off processes with the stakeholders, contributing to code level Unit tests, test … QA systems. You will work with Product Managers, QAEs, SDETs, and SDEs on our internal technology teams to understand features and technical implementation. You will identify use cases, create test plans, define test strategies, and create manual and automated test cases in order to report to stakeholders on the quality and reliability of our products. You will … evangelize quality best practices. You will own creating and driving the test strategy and enforcing designfor testability. This is a role on an exciting new project where you will be the QA on a team driving data collection, identifying user workflows, end-to-end testing, and driving quality improvements. Our ideal candidate: • Defines testMore ❯
