26 to 38 of 38 Electronic Design Automation Jobs in the East of England

Overview: We are looking for an EDA Optimisation Engineer to support the data-driven optimisation, analysis and maintenance of Arm’s engineering platforms. This role will work as part of a team effort to improve system utilisation/efficiency/cost-performance and touch on forecasting accuracy and infrastructure strategy. … finance teams to ensure data-driven decision making. Required Skills and Experience : Background in distributed HPC, cloud environments, data engineering & analytics. Knowledge of EDA workflows and semiconductor engineering environments. Proficiency in Python and data analysis/ML frameworks. Ability to turn sophisticated data into clear, actionable strategy. “Nice To Have ...

week Silicon summer internship, offering hands-on project experience across four specialist teams: RTL, verification, physical design or DFT. You’ll learn advanced EDA tools, tackle real chip development tasks and gain practical silicon engineering skills in a supportive team. Applicants should be pursuing a degree in Electronic ...

deliver high-quality layouts across projects. Responsibilities include planning activities, mentoring engineers, coordinating with silicon, hardware, and manufacturing teams, and advancing automation and EDA tooling to improve efficiency and build quality. #J-18808-Ljbffr ...

open to this role being based in our Cambridge, Manchester or Sheffield offices). Do you want to shape the future of chip design? In the Solutions Engineering group at Arm, we're looking for an experienced physical implementation engineer to join our team in a multi-faceted … performance and cohesiveness of Arm's solutions, while also evolving our next generation of implementation flows. You'll wield influence over the development of EDA tools and contribute to building a proven understanding base surrounding high performance chip design. Within our team, we work with multiple divisions within ...

gain hands-on experience, work on silicon design areas such as RTL, verification, and physical design, and use industry-standard EDA tools. You’ll be mentored while you learn and contribute to real chip development from day one. Starting Sep 2027, this permanent role emphasizes curiosity, problem-solving ...

Limited in Cambridge is seeking an EDA Optimisation Engineer to drive data-driven optimisation, analysis and maintenance of Arm’s engineering platforms. You will help improve system utilisation, efficiency and cost-performance across HPC compute, cloud, Emulation and FPGA environments. In a metrics-first environment, you will develop dashboards, pipelines ...

high-speed circuits, matching constraints, minimisation of parasitics, power grids and ESD requirements Modern semiconductor process technologies including 28nm, 14/16nm, 7nm EDA tools for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop ...

Ltd. Cambridge is seeking an experienced FPGA prototyping engineer to join the team that validates ASIC prototypes before silicon. You will work with design, verification and software teams on RTL adaptation, multi-FPGA partitioning, timing closure and platform bring … full-time Cambridge office role. You will build and maintain prototyping flows, integrate PCIe, LPDDR and Ethernet interfaces, and partner with EDA vendors to resolve tool issues. #J-18808-Ljbffr ...

familiarity with ThinX, HDX, PCoIP, or related protocols. Experience managing distributed Linux environments across on-premises, HPC, hybrid-cloud, or multi-cloud infrastructure. Semiconductor, EDA, or engineering compute experience is helpful. Proficiency in automation using tools such as Terraform, Ansible, Python, Bash, GitLab CI/CD, and REST APIs … Grafana, ELK/OpenSearch, Splunk, CloudWatch, or similar tools. Understanding of SRE and modern operations practices, including incident resolution, capacity management, AIOps, policy-based automation, self-healing services, and operational toil reduction. Contribute to the future evolution of engineering access services through self-service workflows, policy-aware automation ...

hands‐on experience in RTL design, verification, or physical design while contributing to real chip development. You’ll work with industry‐standard EDA tools, learn from experienced colleagues, and build practical skills in timing, verification and SOC integration. This is a permanent, full‐time role with strong learning ...

responsibility for the development and execution of rigorous benchmarks based on real workloads at Arm, across multiple tools and compute platforms. Support partners (especially EDA software vendors), answering technical queries where they have questions relating to porting code or services to Arm. See these through to resolution, potentially over … generate robust measurements of performance. IT Infrastructure awareness: server configuration, networking, storage and datacentre environments. “Nice To Have” Skills and Experience: Understanding of EDA landscape and ideally experience in using tools. Knowledge of Neoverse micro-architectures Experience of Cloud platforms and/or OpenStack Linux Kernel internals. IT Service operations ...

based in Cambridge (also open to Manchester or Sheffield offices). You will shape power, performance and cohesiveness of Arm's solutions and influence EDA tool development to advance high-performance chip design. In this role you’ll work across RTL to GDS2 flows, collaborate with chip design partners ...

experience Bare-metal server and compute environments Kubernetes and containerised infrastructure Terraform/Infrastructure-as-Code Public cloud infrastructure – ideally GCP or AWS Infrastructure automation Networking and storage CPU and/or GPU compute environments Troubleshooting across physical and virtual infrastructure Supporting engineering, scientific or compute-intensive workloads Experience … research/engineering compute environments would be particularly valuable. We're interested in speaking with engineers coming from HPC, scientific computing, semiconductor/EDA, AI infrastructure, research computing or complex enterprise infrastructure environments. #J-18808-Ljbffr ...