1 to 25 of 29 SystemVerilog Jobs in the East of England

that are degree qualified (or equivalent) with significant experience in FPGA development. Competent VHDL Language and Design Skills. Competent Verification Skills using VHDL and SystemVerilog methodologies A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs Experience of professionally configuring and documenting designs Experience of working ...

that are degree qualified (or equivalent) with significant experience in FPGA development. Competent VHDL Language and Design Skills. Competent Verification Skills using VHDL and SystemVerilog methodologies A deep proven level of experience designing for Xilinx, Intel or Microsemi FPGAs Experience of professionally configuring and documenting designs Experience of working ...

development processes Required Skills & Experience Strong experience with FPGA technologies (e.g. Xilinx, Microsemi/Actel, or Lattice) Advanced verification using VHDL and/or SystemVerilog/UVM Expertise in timing constraints and FPGA optimisation Ability to derive detailed firmware requirements from system-level specifications Experience across the full firmware lifecycle ...

development processes Required Skills & Experience Strong experience with FPGA technologies (e.g. Xilinx, Microsemi/Actel, or Lattice) Advanced verification using VHDL and/or SystemVerilog/UVM Expertise in timing constraints and FPGA optimisation Ability to derive detailed xehkeey firmware requirements from system-level specifications Experience across the full firmware ...

tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience with SystemVerilog language Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to memory subsystem ...

Job Description: Salary Range: £45k - £61k Leonardo UK operates a grade-based salary framework with broad bands. The salary range shown reflects the approved grade band for this role, or a narrower hiring range published ...

technical mentorship and support to less experienced engineers. Required Skills and Experience5+ years of experience in IP, subsystem, or SoC verification. Strong proficiency in SystemVerilog and Verilog. Experience with UVM or other industry-standard verification methodologies. Experience developing constrained-random verification environments and reusable verification components. Experience developing verification strategies ...

implementations using VHDL, Simulink and related technologies Design and implement solutions targeting Xilinx, Intel and Microsemi FPGA devices Verify FPGA implementations using VHDL and SystemVerilog/UVM testbench methodologies Use FPGA design toolsets and Mentor verification tools, including QuestaSim and ModelSim Develop low-level software in C to support FPGA … design and development within an engineering, defence or security environment Strong VHDL language and digital design skills Competence in FPGA verification using VHDL and SystemVerilog methodologies Proven experience designing for Xilinx, Intel or Microsemi FPGA platforms Understanding of UVM testbench methodologies and FPGA verification processes Experience using QuestaSim, ModelSim ...

Design, develop and verify FPGA firmware for complex digital systems. Derive firmware requirements and architectures from system-level requirements. Develop RTL using Verilog/SystemVerilog and verify designs using UVM. Work with FPGA toolchains including Xilinx and Intel (Altera) devices. Develop high-speed interface solutions (e.g. PCIe, Ethernet, JESD). … testing and documentation throughout the development lifecycle. Essential Skills & Experience Strong FPGA development experience across major FPGA families. Proficiency with Xilinx tools, TCL, Verilog, SystemVerilog and UVM. Experience with Xilinx 7 Series, UltraScale, Intel (Altera) or Microsemi FPGA architectures. Knowledge of high-speed interfaces such as PCIe, Ethernet and JESD. ...

looking for an FPGA Engineer with the following background: Proven experience in FPGA or ASIC design and verification RTL coding in Verilog or SystemVerilog Familiarity with Vivado or Quartus and timing closure Understanding of system-level design and high-speed electronics Strong academic background in Engineering, Physics, or a related ...

that push boundaries Drive verification efforts with a sharp focus on risk, coverage, and system-level behaviour Key skills Strong hands-on expertise in SystemVerilog and UVM Proven ability to debug across RTL, simulation, and hardware Ability to work effectively with ambiguity and changing requirements Demonstrable commercial experience in functional ...

record delivering complex FPGA systems from concept through to production Strong experience with RTL design, simulation, synthesis and timing analysis, including VHDL, Verilog or SystemVerilog Strong knowledge of high-speed interfaces, DSP, control logic, image processing and hardware-software co-design Excellent technical leadership, communication and stakeholder management skills, with ...

architectures Integration of operating system-class subsystems alongside real-time domains A strong appreciation of the practical realities of chip implementation, including RTL design (SystemVerilog), verification methodologies (UVM, formal, emulation/FPGA), DFT, timing closure, power analysis, and physical design constraints. Familiarity with scripting languages such as Bash, Python ...

functional verification, including ownership of verification planning and strategy. Proven experience of testbench design with verification frameworks like UVM/OVM. Knowledge of SystemVerilog assertion (SVA). Exposure to different programming languages, such as C, C++ and Python. A proactive person who can independently define the scope of work. ...

successful in this role you will also need experience of toolchains such as Vivado or Quartus and a HDL language such as VHDL or SystemVerilog, and experience in running simulations and testbenches and performing hardware-level debugging. The company are offering tailored packages for the right engineer, which includes ...

solve problems more efficiently. Required Skills & Experience: BSc Degree or higher qualification in Electrical Engineering (ECE) or equivalentExcellent understanding of HDLs such as Verilog, SystemVerilog or VHDLVery good knowledge of CPU architecture principles and SoC design principlesKnowledge of System Coherency conceptsAbility to use RTL simulation tools for debugging purposesQuestasim, Verdi ...

cause analysis of issues identified throughout the verification process. Required Skills and Experience :Experience building verification environments for sophisticated RTL designs. Strong proficiency in SystemVerilog and scripting languages such as Python, Perl, or Tcl. Proven grasp of the complete verification process, starting from test planning and continuing through to verification ...

/emulation mismatches and test failures. Hands-on experience with emulation platforms such as ZeBu, Palladium, or Strato. Familiarity with RTL languages such as SystemVerilog/VerilogExperience in collaboration with EDA vendors to introduce new capabilities, resolve tool issues, and contribute to future tool improvements. Skilled in planning system test ...

Digital Verification Engineers. Leaders with the ability to build, recruit and develop a high-performing verification function. Technical Background ASIC/SoC Digital Verification. SystemVerilog and UVM. Functional Verification and Formal Verification. RISC-V processor and SoC verification. Experience leading or managing DV engineering teams. Why Consider This? A rare ...

methodologies, high-quality deliverables and successful project outcomes. Key Responsibilities Develop and execute verification strategies for complex ASIC and FPGA designs. Create and maintain SystemVerilog/UVM verification environments, testbenches and coverage models. Debug RTL and verification issues, ensuring designs meet quality and performance requirements. Collaborate with design, FPGA … reviews. Essential Skills & Experience Degree in Electronic Engineering, Computer Engineering or a related discipline. Proven experience verifying ASIC and/or FPGA designs. Strong SystemVerilog and UVM expertise. Good understanding of RTL design and digital hardware development. Experience with coverage-driven and assertion-based verification techniques. Linux proficiency and scripting ...

engineering team, contributing to the core FPGA technology that powers a range of next-generation products. Responsibilities Design and develop reusable FPGA modules using SystemVerilog for deployment across multiple products. Perform RTL verification and support timing closure through constraints, analysis, and design optimisation. Write module specifications, review code and documentation … maintain high engineering standards. Collaborate with hardware, software, and mechanical engineers to deliver new products to market. Essential Experience Strong SystemVerilog FPGA design experience. RTL verification skills and familiarity with Python. Experience writing timing constraints and achieving timing closure. Desirable Experience Experience with cocotb for FPGA verification. Familiarity with Linux ...

Job Title: Senior Digital Design Engineer Location: Cambridge, United Kingdom Job Type: Permanent Salary: 65K - 88K GBP per annum DOE Role Overview: Work at the forefront of open silicon and hardware security, contributing to next ...

Job Overview: Arms Solution Engineering division develops SoCs for various application segments, using the latest IP products from Arm and other vendors. We are looking for a creative and hard-working SoC Design Engineer to ...

The roleThis is a unique opportunity to leverage your silicon design skills on cutting-edge technology. At Imagination Technologies, innovation is at the heart of everything we do. We create foundational building blocks for market ...

About SiFiveAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications ...