4 of 4 FPGA Jobs in County Antrim

Senior IP Design Engineer

Hiring Organisation
Infoplus Technologies UK Ltd
Location
Belfast, County Antrim, Northern Ireland, United Kingdom
Employment Type
Contract
Contract Rate
From £300 to £450 per day
Description: Role: Senior IP Design Engineer Type: Contract Location: Belfast, UK Hybrid Job details: Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Key Skills: SystemVerilog RTL design 100Gb Ethernet, PCIe Gen5, AMBA/AXI Deep understanding … FPGA/Adaptive SoC design flow including P&R and timing closure Vivado/Vitis expertise Python/Tcl scripting Git & CI/CD experience ...

Senior IP Design Engineer

Hiring Organisation
Infoplus Technologies UK Ltd
Location
Belfast, UK
Description:Role: Senior IP Design EngineerType: ContractLocation: Belfast, UK Hybrid Job details: Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements.Key Skills:SystemVerilog RTL design100Gb Ethernet, PCIe Gen5, AMBA/AXIDeep understanding xkybehq of FPGA/Adaptive ...

Senior IP Design Engineer

Hiring Organisation
Infoplus Technologies UK Ltd
Location
Belfast, United Kingdom
Employment Type
Contract
Contract Rate
GBP 300 - 450 Daily
Description: Role: Senior IP Design Engineer Type: Contract Location: Belfast, UK Hybrid Job details: Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Key Skills: SystemVerilog RTL design 100Gb Ethernet, PCIe Gen5, AMBA/AXI Deep understanding … FPGA/Adaptive SoC design flow including click apply for full job details ...

Senior IP Design Engineer

Location
Belfast, County Antrim, United Kingdom
span span style="" b Job details:/b/span/span/div div style="" span span style="" Design high-performance IP targeting FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements./span/span/div div style="" span … span span style="" 100Gb Ethernet, PCIe Gen5, AMBA/AXI/span/span/div div style="" span span style="" Deep understanding of FPGA/Adaptive SoC design flow including.../span/span/div div style="" br// ...