Staff Design Verification Engineer
- Hiring Organisation
- AMD
- Location
- Cambridge, Cambridgeshire, United Kingdom
- Salary
- £ 70 K
memory subsystems would be a plusProficient in debugging firmware and RTL code using simulation tools Proficient in using C++ testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ CPU pipeline knowledge Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency … improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience with SystemVerilog language Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure ...