Design Verification Engineer
Reading, England, United Kingdom
IC Resources
constrained random verification - Functional and code coverage analysis SystemVerilog Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Formal verification and verification qualification techniques Scripting experience with Ruby, sh/csh, TCL, Make, Perl - advantage This is a hybrid more ยป
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