8 of 8 PCIe Jobs in London

design experience in timing-critical systems.Strong background in SystemVerilog, synthesis, timing closure and verification.Hands-on with Vivado/Quartus or equivalent toolchains.Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces.Bonus skills for aSenior FPGA Engineer:Exposure to high-performance computing, networking or real-time data systems.Knowledge of C/ ...

Equipment e.g ScopesHard Real-Time embedded software developmentExperience of Real Time Operating Systems e.g FreeRTOSDesirable, but not essential:Communication Protocols (e.g. SPI, UART, Ethernet, PCI-Express)Experience in model-based development, using UML or using tools such as IBM's RhapsodyStrong problem solving at system and software component level ...

teams to ensure quality and performance targets are met.Skills, Experience, and Abilities Required:Expertise in System Verilog RTL designHands-on experience with 100Gb Ethernet, PCIe Gen5, AMBA/AXIIn-depth knowledge of FPGA/Adaptive SoC design flow, including place & route (P&R) and timing closureProficiency in Vivado/VitisStrong ...

software integration Familiarity with AMD Adaptive SoC development tools, including: AMD Vivado AMD Vitis High-Speed Networking Experience Hands-on experience with: 100Gb Ethernet PCIe (various generations) Understanding of high-throughput, low-latency networking architectures Development Workflow Competence Proficiency with Git , including branching strategies, code review, and CI/ ...

system levelKeeping designs under configuration controlProviding progress reportsThe Individual Were looking for people who can show:High-speed serial communication interfaces/protocols (e.g. PCIe, Ethernet/IEEE802.3, SPI, I2C, etc.) and high-speed bus architectures (e.g. DDR3/4)Use of high-speed digital design techniques such as signal ...

architecture, integration, timing closure, place-and-route (P&R), constraints and optimisation. The role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows.Key ResponsibilitiesDesign high-performance IP using SystemVerilog … FPGA/Adaptive SoCDeliver synthesis-ready RTL meeting timing, P&R and integration requirementsImplement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocksDrive timing closure using Vivado toolchainsDevelop automation using Python/Tcl scriptingCollaborate with hardware, SoC, firmware and integration teamsEssential SkillsStrong SystemVerilog RTL design experienceFPGA/Adaptive ...

environments.Key ResponsibilitiesDesign and implement UVM/SystemVerilog verification environmentsDeliver constrained-random verification and achieve coverage sign-offVerify high-speed interfaces including Ethernet (100G) and PCIe (Gen4/Gen5)Integrate and use Verification IP (VIP)Develop and maintain Python-based regression and CI workflowsCollaborate with design, architecture, and SoC teamsEssential Skills … ExperienceStrong experience as a Verification Engineer/Design Verification EngineerExpert knowledge of UVM and SystemVerilogExperience with Ethernet, PCIe, AMBA/AXIProven ownership of test plans and coverage closurePython scripting and Git-based workflowsExperience in ASIC, SoC, or IP verification environmentsDesirableExperience with Vivado/Vitis or adaptive SoC flowsEmbedded processor ...

Location: Malvern, Worcestershire, West Midlands, UKYT Tech are on the lookout for a FPGA DSP engineer for a company in Malvern.Thecompanyareinthedefenceindustryandarelookingforsomeonetocontribute with a lot of design and development of system and subsystems and RF signal ...