driver development Comprehensive understanding of clock domain crossing techniques Strong knowledge of FPGA tool flows (synthesis, partitioning, place&route, timing analysis) Excellent skills in SystemVerilog/Verilog/VHDL Experience in scripting (tcl preferable) and Python programming Experience using Questa, ModelSim, GHDL, Verilator, cocotb Experience using Quartus/Vivado/ more »
Electrical/Electronic Engineering or a related field. Brings 3+ years of hands-on experience in RTL design and verification for FPGAs, mastering Verilog, SystemVerilog, or VHDL. Proficient in FPGA toolchains, especially with Xilinx Vivado (preferred) or Intel Quartus. Skilled in simulation environments, preferably with expertise in Modelsim/Questa. more »
s degree in Electrical/Electronic Engineering or related field. 2 - 10 years of experience in RTL design and verification for FPGAs using Verilog, SystemVerilog, or VHDL. Experience with Vivado/Quartus A Software Engineering and Hardware Engineering background is a plus Desirable Skills: Knowledge of networking protocols, such as more »
ASIC Hardware Design Engineer - UK This position is a unique opportunity to exercise your ASIC design skills on cutting edge designs. The successful ASIC Design Engineer will have the opportunity to join a business who design the key building blocks more »
Contract Firmware Engineer London/Remote 6-month Contract £65 - £70 per hour (Outside IR35) Are you ready for a new contract with a global aerospace business? IO Associates are seeking a new Firmware Engineer to work alongside the expertise more »
ASIC Design Engineer – AI Start Up London HQ Remote (UK) option can be considered. Based in London, my client is an extraordinary early-stage start-up seeking an ASIC Engineer who has the potential to fast track to lead and more »
ASIC Design Engineer - AI Start Up London HQ Remote (UK) option can be considered. Based in London, my client is an extraordinary early-stage start-up seeking an ASIC Engineer who has the potential to fast track to lead and more »
