10 of 10 Senior Verification Engineer Jobs in the East of England

Senior Verification Engineer Department: Hardware Employment Type: Full Time Location: Cambridge Description Our RTL team delivers efficient ASIC and FPGA implementations of advanced communications algorithms, working across IP development, integration and verification. To support this work, we are looking for a Senior Verification Engineer to support the complete UVM verification of Accelercomm IP. Purpose : Responsible for verification of RTL implementations for advanced wireless communications IP and modem subsystems, ensuring designs meet functional, performance and quality requirements prior to FPGA deployment and ASIC tape-out. Key Responsibilities Develop verification plans from ...

AccelerComm Ltd in Cambridge is seeking a Senior Verification Engineer to lead RTL verification of advanced wireless IP for ASIC and FPGA implementations. You will develop verification plans, build SystemVerilog/UVM environments and ensure coverage and quality before tape-out. The role requires 3+ … years in digital verification, strong SV/UVM, Linux scripting, and experience with coverage-driven methods. A hybrid work model in Cambridge is available with competitive compensation. #J-18808-Ljbffr ...

AccelerComm Ltd in Cambridge is seeking a Senior Verification Engineer to lead RTL verification of advanced wireless IP and subsystems. You will develop verification plans, create SystemVerilog/UVM environments and build testbenches, assertions and coverage models for complete UVM verification. The role requires strong … SystemVerilog/UVM skills, RTL design understanding, Linux scripting and a proactive, collaborative mindset to drive automation, CI and verification sign-off across teams. #J-18808-Ljbffr ...

Intellectual Capital Resources Ltd in Cambridge is seeking a Senior Verification Engineer to join a rapidly growing HW team. You will work on cutting-edge technology in quantum computing and learn alongside world-class engineers in a cross-disciplinary environment. You will own verification across block … subsystem, and multi-FPGA designs, develop scalable UVM testbenches and define the verification strategy in collaboration with the Lead Verification Engineer. #J-18808-Ljbffr ...

Surgical in Cambridge is seeking a Senior System Verification Engineer to support system level verification for new designs and formal verification activities. You'll define and execute test protocols, lead verification engineers, and ensure compliance with health and safety regulations. The ideal candidate ...

Qualcomm Technologies International Ltd in Cambridge seeks an ASIC Verification Engineer specializing in Formal Property Verification (FPV) to join the Engineering Group > ASICS Engineering. You will develop FPV test plans, write SystemVerilog Assertions, and collaborate with global RTL design and DV teams to drive sign-off. … role requires 2+ years in ASIC design/verification, a degree in Science/Engineering (BS/MS/PhD), and hands-on FPV tool experience with JasperGold/VC Formal. #J-18808-Ljbffr ...

they make technological breakthroughs in security with a product line built on CHERI technology and RISC‐V cores. I am looking for Verification Engineers between 8-16 years experience to join a talented team. You will work in an environment where you are not pigeon holed … brings over 30 years of semiconductor experience from world renown companies and start-ups. Responsibilities Collaborates with the design team to understand and define verification requirements for security features Develops and maintains verification plans, testbenches, and test scenarios using UVM methodology Executes test plans and verifies the correctness ...

data paths, block functionalities & interfaces; Prior knowledge of GPU Architecture is a big plus. Hands-on experience in strategizing, brainstorming, and developing Formal Property Verification (FPV) test-plan, developing an assertion-based verification testbench, debugging all RTL artefacts, and achieving formal sign-off matrices is a MUST. Collaborate … skills, ability to learn, improve, and deliver Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation ...

Intellectual Capital Resources Ltd is seeking Verification Engineers in the United Kingdom with 8–16 years of experience to join a high‐performance team. You will define verification requirements for security features, develop UVM testbenches, and verify CHERI‐based security capabilities across FPGA/ASIC flows. You will ...

pride in tackling hard problems with curiosity, humility, and a deep sense of care for one another. Our growing team is looking for a Senior/Staff Physical Verification and PDK Engineer to own physical verification and design enablement for our most advanced heterogeneous integration program. … electro-optic device experience are not required. We have deep in-house expertise and will teach you. We are hiring specifically for commercial physical verification and design enablement skills, and we welcome strong candidates from an electronic IC background. As part of your responsibilities, you will: Either 6+ years ...