Desirable/Optional) Working with version control and project management/bug tracking systems such as SVN/Git and Jira. Xilinx FPGA technology. Synopsys tool flows. Experience using Arm DS5/DSTREAM debugger (Desirable/Optional) Excellent written and spoken English; can write coherent documentation more »
Farnborough, Hampshire, South East, United Kingdom
Hays
Practical use of scripting languages Tcl/Python/Perl etc Experience of at least one of the following EDA tool flows: Cadence or Synopsys Communicating with other design teams, 3rd party IP and library suppliers and EDA tool vendors to improve scripts and tool flow Managing/Interfacing to more »
at wafer- and package-level; A good understanding of statistical analysis and design of experiments; Knowledge of semiconductor TCAD tools for device simulation, i.e. Synopsys Sentaurus, Silvaco Victory; Background in electronics engineering for system understanding in the field of power electronics. Excellent problem-solving skills – able to identify problems and more »
synthesis, STA, test insertion, MBIST, formality, GDS layout etc Experience in EDA tools for custom IC development like Siemens Questa for simulation and verification, Synopsys DesignCompiler for synthesis and STA, Spyglass for linting, etc. Experience in writing IP design specifications and block level modules Good knowledge of UVM, SVA, VIP more »
depending on experience) What you need to be successful in this role: Experience writing Hardware description languages ideally SystemVerilog Experience using EDA simulators (Siemens, Synopsys, Cadence) Experience working with version control and code review systems (Git, Gerrit) Experience with CI (Jenkins) Scripting for design automation (Python, Perl, JSON, Tcl, Make more »
Farnborough, Hampshire, South East, United Kingdom
Hays
testing. Hierarchical/Flatten Flow: Experience managing hierarchical and flatten design representations. ATPG Generation: Skill in generating Automatic Test Pattern Generation (ATPG) patterns. SDC (Synopsys Design Constraints) Support: Provide full SDC support for the physical team, ensuring seamless timing closure from synthesis to full-chip flatten Static Timing Analysis (STA more »
conductor/Semi-conductor/GPU/SystemVerilog/System Verilog Assertions/Property Specification Language/Cadence/JasperGold/Siemens EDA/Synopsys If you are interested in this Formal Verification Engineer position, please send a CV to ts@eu-recruit.com By applying to this role you understand more »
Reading, Berkshire, South East, United Kingdom Hybrid / WFH Options
Technical Futures
A Semiconductor industry DFT Engineer will take responsibility for driving the design implementation and simulations through to successful tape-out for an innovative leader in high speed chip to chip link solutions; revolutionizing the electronics industry. Can be based in more »
