6 of 6 SystemVerilog Jobs in the City of London

youll do Define FPGA microarchitecture with a cross-functional team Implement RTL, including synthesis, timing closure, and debug Develop and execute unit-level verification (SystemVerilog) Build and validate FPGA prototypes for internal testing and click apply for full job details ...

testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python and/or C++ for building verification infrastructure, tooling, and automation. ...

youll do Define FPGA microarchitecture with a cross-functional team Implement RTL, including synthesis, timing closure, and debug Develop and execute unit-level verification (SystemVerilog) Build and validate FPGA prototypes for internal testing and customer trials What theyre looking for Strong industrial experience in high-speed FPGA design Hands … experience with high-end FPGA platforms Excellent RTL skills (SystemVerilog/Verilog/VHDL) Strong PCIe experience Broader software exposure (C/C++, Python) If you have the right skills and experience, wed love to hear from you! Apply today with your updated ...

youll do Define FPGA microarchitecture with a cross-functional team Implement RTL, including synthesis, timing closure, and debug Develop and execute unit-level verification (SystemVerilog) Build and validate FPGA prototypes for internal testing and customer trials What theyre looking for Strong industrial experience in high-speed FPGA design Hands … experience with high-end FPGA platforms Excellent RTL skills (SystemVerilog/Verilog xkybehq/VHDL) Strong PCIe experience Broader software exposure (C/C++, Python) If you have the right skills and experience, wed love to hear from you! Apply today with your updated ...

areas like memory, interconnect, and high-speed interface design. Key Responsibilities: Develop and integrate designs of RTL for digital blocks (using Verilog/SystemVerilog/VHDL) Undertake Digital IC Design processes & perform design synthesis, linting Complete projects from conception to completion Skills Required: Experience with frontend RTL Design Strong Experience … with SystemVerilog, Verilog, or VHDL Has had exposure to ASIC design flow (Lint, synthesis, simulation) Digital Design Principles experience – pipelining, clock domain crossing Further Details: This role offers remote working with a potential visit the office every month. A competitive salary, bonus scheme, and a strong benefits package. ...

with quarterly visits to London. What You’ll Do Own unit‐level and core‐level verification for complex digital IP Build scalable SystemVerilog/UVM environments Develop constrained‐random and directed tests to drive high coverage Debug failures across RTL, testbench, and micro‐architecture Automate regressions and flows using Python … with modern IP ecosystems: microprocessor cores, memory subsystems, AMBA interconnects, system debug logic What You Bring 3–4+ years of digital verification experience Strong SystemVerilog/UVM expertise Solid understanding of digital logic and verification methodologies Experience with ARM‐based components (M‐class cores, NIC, Coresight, AMBA protocols) Familiarity with ...