26 to 26 of 26 SystemVerilog Jobs in Edinburgh

development lifecycle. This is a hands-on verification role covering everything from planning and testbench development through to coverage closure and debugging. Responsibilities Develop SystemVerilog and UVM verification environments Create reusable verification components and testbenches Write assertions and functional coverage Debug complex RTL and simulation issues Drive verification activities from … sign-off Work closely with cross-functional engineering teams Help improve verification methodology and best practice About You You'll ideally have experience with: SystemVerilog UVM ASIC or SoC Verification Functional Coverage SystemVerilog Assertions (SVA) RTL Debug Verification Planning Experience within automotive or safety-critical semiconductor development would be beneficial ...