of verifying CPU architectures or other complex IP (e.g. GPUs, NNAs) Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Past verification ownership of a design block Analytical thinking, self-sufficiency and team collaboration skills Ability to work effectively across More ❯
Bristol, Gloucestershire, United Kingdom Hybrid / WFH Options
Codasip
of own work YOU SHOULD HAVE: Over 5 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning More ❯
level simulation etc ) Knowledge of verifying CPU architectures or other IP Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go Analytical thinking and team collaboration skills What we'd love you to have Past verification ownership of a design block More ❯
/PCIe/CXL, DDRx/LPDDRx integration verification in SoC RTL. Your key responsibilities will include writing test plans, defining test methodologies, developing SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, setting schedules, and quality More ❯
Sondrel is looking for an experienced Verification Engineers to join our global team. In this hands-on technical role, you will contribute to a variety of SoC, subsystem, and IP development projects, taking responsibility for the verification process from planning More ❯
throughout the full chip design life cycle from architecture definition to sign-off and post-silicon validation Write thorough design specifications Author high-quality SystemVerilog following engineering best practices Participate with verification team on test plan definition, debug, and coverage closure Ensure high-quality full-system design functionality while upholding … degree in Electrical Engineering or Computer Science, or a related technical field or equivalent experience 4 years of experience with architecture and design of SystemVerilog-based chips and IP blocks Experience with design flows including lint, synthesis and timing closure (e.g. SDF) Experience with multipower and multiclock domain designs Preferred More ❯
