5 of 5 SystemVerilog Jobs in Peterborough

Staff RTL Design Engineer

Hiring Organisation
Jobleads-UK
Location
Cambridgeshire and Peterborough, England, United Kingdom
equivalent industry experience). 6+ years’ experience in RTL design. Academic or commercial experience in CPU RTL design. Strong RTL design skills using Verilog, SystemVerilog, or VHDL. A solid software engineering background, including experience with: Object‐oriented and functional programming paradigms – C, C++, Python Compiler infrastructures, particularly domain‐specific languages ...

Staff Verification Engineer

Hiring Organisation
Jobleads-UK
Location
Cambridgeshire and Peterborough, England, United Kingdom
cross‐functional hardware teams Debug challenging issues spanning RTL, simulation, and hardware platforms What they’re looking for Strong hands‐on expertise in SystemVerilog and UVM Proven debugging skills across RTL, simulation, and hardware Experience owning verification planning and strategy in commercial environments Comfortable operating in fast‐moving environments with ...

Principal ASIC Design Engineer

Hiring Organisation
Jobleads-UK
Location
Cambridgeshire and Peterborough, England, United Kingdom
architectures Integration of operating system-class subsystems alongside real-time domains A strong appreciation of the practical realities of chip implementation, including RTL design (SystemVerilog), verification methodologies (UVM, formal, emulation/FPGA), DFT, timing closure, power analysis, and physical design constraints Familiarity with scripting languages such as Bash, Python ...

Staff CPU RTL Design Engineer – High-Performance Cores (Equity)

Hiring Organisation
Jobleads-UK
Location
Cambridgeshire and Peterborough, England, United Kingdom
leading processor designs and collaborating with top architects and engineers. The role requires 6+ years in RTL design and strong skills in Verilog/SystemVerilog/VHDL, with exposure to verification methods like UVM. #J-18808-Ljbffr ...

Lead Verification Engineer — IP/SoC Testbenches (UK Onsite)

Hiring Organisation
Jobleads-UK
Location
Cambridgeshire and Peterborough, England, United Kingdom
Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi‐chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans … Engineering or Computer Science 6+ years and current hands‐on experience in block‐level/IP‐level/SoC‐level verification Proficiency in Verilog, SystemVerilog Familiarity with industry‐standard EDA tools for simulation and debug Deep experience with UVM‐based testbenches Experience with modern programming languages like Python Knowledge ...