6 of 6 Tcl Jobs in the South East

and verification, including: Defining functional requirements for verification environments & metrics SystemVerilog UVM testbenches Formal proof verification Understanding of C test cases and C code Scripting languages (e.g. Python, Perl, TCL) Desirable Skills Experience with formal verification tools (JasperGold, VC Formal) Familiarity with C/C++ development Prior SSD experience with storage interfaces such as SAS or PCIe (NVMe preferred) What More ❯

and verification, including: Defining functional requirements for verification environments & metrics SystemVerilog UVM testbenches Formal proof verification Understanding of C test cases and C code Scripting languages (e.g. Python, Perl, TCL) Desirable Skills Experience with formal verification tools (JasperGold, VC Formal) Familiarity with C/C++ development Prior SSD experience with storage interfaces such as SAS or PCIe (NVMe preferred) What More ❯

Configuration Vectors etc. Programming and scripting languages, particularly writing and debugging Linux/Unix bash scripts is an advantage. Knowledge of a programming language such as C, Java, python, TCL, VBA would be useful. Competent in the use of various test equipment used for electrical measurements, e.g. DMM, oscilloscope, current probes, Data acquisition unit, data bus monitors (1553 MilBus and More ❯

Engineers for contracts based in Luton, Bedfordshire. The Firmware Engineer will deliver Firmware for complex digital systems that meet challenging future customer requirements. Responsibilities Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet, and JESD is also required. More ❯

verification experience Vast experience of: Translating design requirements into RTL Deriving functional requirements for verification Systemverilog UVM test benches Scripting languages & REST API’s (e.g. Perl/Python/TCL) Team player with good verbal and written communication skills Verification Engineer Desirable skills: Experience of Formal Verification (Jasper Gold or VC_Formal) Experience using SV UVM 1800.2 Familiarity with C More ❯

verification experience Vast experience of: Translating design requirements into RTL Deriving functional requirements for verification Systemverilog UVM test benches Scripting languages & REST API’s (e.g. Perl/Python/TCL) Team player with good verbal and written communication skills Verification Engineer Desirable skills: Experience of Formal Verification (Jasper Gold or VC_Formal) Experience using SV UVM 1800.2 Familiarity with C More ❯