17 of 17 Tcl Jobs in the UK excluding London

work you ll be required to be eligible to obtain a high level of UK Security Clearance Responsibilities : Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM FPGA architectures such as Xilinx 7. Xilinx UltraScale; Intel (Altera) or Microsemi (Actel). Fast interfaces such as PCIe, Ethernet ...

design reviews, testing and documentation throughout the development lifecycle. Essential Skills & Experience Strong FPGA development experience across major FPGA families. Proficiency with Xilinx tools, TCL, Verilog, SystemVerilog and UVM. Experience with Xilinx 7 Series, UltraScale, Intel (Altera) or Microsemi FPGA architectures. Knowledge of high-speed interfaces such as PCIe, Ethernet ...

optimisation low level software, firmware and embedded requirements - drivers, controllers etc. Confident knowledge of a variety of coding languages - C, C++, system C, TcL, python Excellent communications, and ability to work across software and hardware teams Nice to have skills Team leadership/management SOC performance & modelling - C, C++, system ...

design through to verification Experience with Xilinx Zynq or similar SoC platforms Understanding of timing closure and high-speed digital design Desirable Python or Tcl scripting MATLAB High-Level Synthesis (HLS) Video interfaces (MIPI, SDI) C++ Functional Safety (IEC 61508/ISO 26262) Defence, aerospace or other safety-critical industries ...

Ethernet, OCP, Wishbone, JESD204, CameraLink, or SMPTE. Experience using tools such as DOORS, Vivado, ModelSim, Diamond, Radiant, Vitis, or Propel. Ability to script using TCL or other scripting languages. Solid understanding of DO-254 processes. Experience working as part of an Integrated Product Team would be advantageous. Required Skills Strong ...

Proficiency with Cadence tool suite, such as Xcelium/IMC/Virtuoso etc. Verification planning tools (ePlanner/vManager) and scripting languages (Shell/TCL/Perl/Python). An understanding of FPGA prototyping/tools, and supporting development of necessary scripting and pre-silicon validation. Experience with multiple ...

Verilog or VHDL. Exposure to all stages of design: concept, specification, implementation, testing, documentation, and support. Proficiency in UNIX and scripting languages such as TCL, Perl, Python, or shell scripting. Prior technical and/or team leadership skills required for more senior positions. Desirable skills and experience Knowledge of advanced ...

Verilog or VHDL. Exposure to all stages of design: concept, specification, implementation, testing, documentation, and support. Proficiency in UNIX and scripting languages such as TCL, Perl, Python, or shell scripting. Prior technical and/or team leadership skills required for more senior positions. Desirable skills and experience Knowledge of advanced ...

Formal). Experience of design best practices and HW/FW interfaces. Strong working knowledge of digital design and SoC architecture. Scripting in Perl, TCL or Python. Gate‐Level Simulation and Debug — 0‐delay, timing annotated. Experience in Low power aware Verification. Debugging regression failures and tracking to closure through ...

experience Knowledge of FPGA toolchains (Vivado, Quartus, ModelSim) Experience with SoC devices (e.g. Zynq UltraScale+) Desirable: Video/RF protocols (MIPI, SDI) Python or TCL scripting High-reliability, defence, or aerospace experience UK Security Clearance (SC or DV) This FPGA Engineer job offers the chance to develop in a very ...

VHDL and familiarity with modern digital design flows. Strong ability to diagnose and resolve complex design issues, including via scripting/programming (Python, Tcl, etc.). Demonstrated excellence in cross functional leadership and communication across global teams. Strong organisational skills with ability to manage multiple priorities and drive execution ...

RedHawk, Conformal). Ability to debug complex physical design issues across timing, congestion, clocking, routing, power, and verification domains. Scripting and automation experience using TCL, Python, or Perl. Strong communication skills and the ability to work effectively in a global, cross‐functional engineering environment. Minimum Qualifications Bachelor’s degree ...

clock power optimization. Familiarity with multi‐corner multi‐mode timing closure and variation‐aware implementation methodologies. Experience developing automation or analysis flows using TCL, Python, Perl, or similar scripting languages. For Staff‐level candidates, demonstrated ability to lead technical initiatives, influence cross‐functional teams, define methodology, and mentor other engineers. ...

automation Good understanding of ARM Cortex-M series processors and CPU architecture Some PCB electronics design experiences Familiarity with Linux, Git, Bash, and Tcl Compensation: Private health insurance Life insurance 33 days holiday Expert training from renowned industry veterans Apply now to join a company truly leading their niche ...

validation Radiation effects and mitigation techniques DC/DC power supply design Environmental, thermal and EMI/EMC standards Scripting languages such as Python, Tcl or Perl Previous experience leading engineering teams or line management What's on Offer Work on innovative space and satellite technologies with real-world impact. ...

meet any or all the following additional requirements: Experience with version control e.g. Git/SVN Experience with tool chain scripting e.g. tcl/python. Reasonable Adjustments: Respect and equality are core values to us. We are proud of the diverse and inclusive community we have built, and we welcome ...

Vivado, Quartus or Libero) and version control (GIT/SVN/CVS). For experienced candidates: proven end-to-end FPGA delivery, interface definition, TCL scripting, and robust verification approaches (e.g. UVM/OSVVM/ABV). Bonus points for: experience with Xilinx/Intel (Altera)/Microchip devices; ModelSim …/Graduate Hardware Engineer/Electronics Engineer/VHDL/Verilog/SystemVerilog/Vivado/Quartus/Libero/ModelSim/QuestaSim/TCL/Xilinx/Intel (Altera)/Microchip (Microsemi)/UVM/OSVVM/Assertion-Based Verification/USB 3.2/NVMe/Layer-2/ ...