3 of 3 UVM Jobs in Cambridge

growing team. Key Responsibilities Lead digital IC verification activities through tape-out and sign-off. Develop and enhance Python-based verification environments (non-UVM). Ensure high-quality, production-ready IC designs. Support verification across IC (silicon) and FPGA (emulation) platforms. Own verification coverage, lint, and quality sign-off processes. ...

occasional onsite support to VIP users in Arm offices across the world as and when required Required Skills & Experience: Experience of using SystemVerilog and UVM with sound understanding of object-oriented design, data structures and algorithms Experience of IP and SoC verification with deep knowledge of verification processes and methodologies ...

experienced engineers, helping to develop robust verification environments while gaining exposure to production silicon and advanced verification methodologies. Responsibilities Develop and debug SystemVerilog/UVM testbenches. Create and execute verification plans, tests, and coverage. Debug simulation failures and support regression testing. Contribute to verification infrastructure and automation. Collaborate closely with ...