2 of 2 UVM Jobs in Cambridge

collaborative person who actively shares feedback and can independently define the scope of work. Proven experience of testbench design with verification frameworks like UVM/OVM. Knowledge of SystemVerilog assertion (SVA). Exposure to different programming languages, such as C, C++ and Python. Even better if You have formal verification ...

Responsibilities: Develop and execute UVM testbenches for unit-level and sub-system verification Perform coverage analysis and drive coverage closure to ensure verification completeness Work with PCIe, AMBA CHI, and AXI protocols for system verification Collaborate with design and verification teams to ensure timely delivery of high-quality designs Required … Skills & Experience: Strong experience with PCIe protocol verification Expertise in UVM methodology for both unit-level and sub-system level verification Hands-on experience with AMBA CHI & AXI interfaces Proven experience in coverage analysis and closure Strong problem-solving and debugging skills in a collaborative team environment Working Pattern ...