1 of 1 UVM Jobs in Cambridgeshire

cores, OTBN (cryptographic CPU), AES accelerators, and peripherals like USB, I2C, and SPI. Key Responsibilities Design, implement, and debug block/system-level tests and testbenches using SystemVerilog and UVM Develop test and coverage plans for new and updated designs Triage and debug nightly regressions Review contributions to open-source projects Enhance test and CI infrastructure Collaborate on academic/… industry publications Stay current with verification best practices and introduce improvements Candidate Requirements Essential: 5+ years industry experience in design verification Strong SystemVerilog and UVM expertise Experience across the full verification cycle (planning to tape-out) Able to provide estimates and coordinate with project managers Comfortable in multidisciplinary, multi-organisation teams Familiar with Git and code review tools (GitHub, GitLab More ❯