21 of 21 UVM Jobs in Cambridgeshire

Skills and Experience: Experience with ARM-based designs and/or ARM System Architectures. Familiarity with ARM debugger and trace features e.g ARM DS, DSTREAM. Experience with verification methodologies - UVM/OVM. Knowledge of PCIe and CXL will be a plus. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation More ❯

formal verification. System C design and High-Level Synthesis flows. Experienced with RTL and Gate-Level power analysis. Knowledge and experience of defining HW/FW interfaces. Experience of UVM based verification tests is desirable. Ability to automate and improve process through scripting in Python, Perl or similar. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. More ❯

M and IoT IP and SoCs, including: Ability to analyze HW design spec and develop verification test plan/strategy Test bench and infrastructure development using System Verilog and UVM IP level test development using System Verilog and UVM IP level test development using Formal Methods SoC level test development using System Verilog and embedded C code Contribute to requirements … will provide targeted on the job training. Excellent communication skills a must. Skills and Experience We Would Love to See: Experience of System Verilog, Verilog or VHDL Experience of UVM (optional) Experience of C or other high-level languages Knowledge of Standard interfaces, Bus protocols and Processor architectures Enthusiasm to learn in a fast-paced environment. Desirable: Python programming a More ❯

analytical skills, responsibility, and problem-solving capabilities. You might also have: Understanding of verification requirements through specification analysis. Experience in GPU/CPU design and associated tools such as UVM or formal verification methodologies. Knowledge of CPU, DSP, or FPU architectures and debugging/testing strategies. Hands-on experience with ASIC, FPGA, and physical design tools (P&R). Proficiency More ❯

About Us Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools More ❯

Version control systems like perforce, git etc would be critical. Understanding of Logic Equivalence, CDC, Lint, UPF/CLP checks would be a plus. Familiarity with System Verilog and UVM would be a plus. Exposure to post-silicon testing and tester pattern debug are major assets. Strong problem solving and debug skills across various levels of design hierarchies. Must have More ❯

of unit verification, including collecting requirements, defining test methodologies, writing test plans, developing testbenches and test cases, and driving verification closure. Strong hands-on experience in System Verilog and UVM methodology, with a solid background in Object-Oriented programming. Proven ability to debug complex designs and verification environments. Experience owning verification environments across multiple stages of verification, from investigation to More ❯

features utilizing CHERI technology. Responsibilities Collaborates with the design team to understand and define verification requirements for security features Develops and maintains verification plans, testbenches, and test scenarios using UVM methodology Executes test plans and verifies the correctness of hardware security features Works closely with the cross-functional teams to ensure the implementation meets design specifications and security requirements Identifies … manner Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Strong understanding of hardware verification methodologies and tools Experience with UVM (Universal Verification Methodology) for FPGA/ASIC verification Familiarity with security features and protocols, such as CHERI, is a plus Excellent communication skills and the ability to work effectively in a collaborative More ❯

features utilizing CHERI technology. Responsibilities Collaborates with the design team to understand and define verification requirements for security features Develops and maintains verification plans, testbenches, and test scenarios using UVM methodology Executes test plans and verifies the correctness of hardware security features Works closely with the cross-functional teams to ensure the implementation meets design specifications and security requirements Identifies … manner Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field Strong understanding of hardware verification methodologies and tools Experience with UVM (Universal Verification Methodology) for FPGA/ASIC verification Familiarity with security features and protocols, such as CHERI, is a plus Excellent communication skills and the ability to work effectively in a collaborative More ❯

responsible for ensuring the exceptional quality of complex graphics IP designs. You will collaborate with multi-functional teams to tackle new challenges, requiring robust written and verbal abilities.Using SystemVerilog, UVM, C++, and scripting languages, you will develop test benches, generate tests, run and debug simulations to drive our complex graphics IPs to high-quality closure.As you progress, you'll take More ❯

Engineer, Senior : Design Verification of custom V&M and IoT IP and SoCs, including: Design analysis for testability Test planning Test bench and infrastructure development using System Verilog and UVM IP level test development using System Verilog and UVM IP level test development using Formal Methods SoC level test development using System Verilog and embedded C code Work is in … a dynamic team environment. Skills and Experience we would love to see Experience of System Verilog, Verilog Experience of UVM Experience of C or other high-level languages SV-UVC development UVM testcase development Strong debug skills Knowledge of Standard interfaces, Bus protocols and Processor architectures Proven track-record of delivering quality verification on time Enthusiasm to learn in a … Qualifications Education: Masters - Computer Engineering, Masters - Computer Science, Masters - Electrical Engineering Work Experiences: 3 yrs+ in an appropriate Design Verification role, with hands-on experience of designing and coding UVM UVCs and test cases. Skills: System Verilog, UVM, Embedded C, Design Verification, Python WE INVENT THE TECH THE WORLD LOVES, SO IF YOU ARE INTERESTED IN LEARNING MORE What's More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

and RTL at IP or SoC level. Proficiency in ASIC/FPGA design tools and optimization techniques. Strong analytical and problem-solving abilities. Preferred Skills: Experience with verification methodologies (UVM, assertions, formal verification). Knowledge of CPU/GPU/DSP architectures. Proficiency in SystemVerilog, C, Python, or scripting languages. More ❯

across block-level and system-level designs Core skills Strong commercial experience in functional verification , with ownership of verification strategy and planning Expertise in testbench design using frameworks like UVM or OVM Proficiency with SystemVerilog assertions (SVA) Familiarity with multiple programming languages (e.g., C, C++, Python ) Visa sponsorship will be provided for candidates who require. Please note, you must already More ❯

packages and driving them to success. Required Skills and Experience: Meticulous attention to detail, ensuring high-quality verification that minimizes bug escapes. Shown experience in block-level verification using UVM or similar methodologies. Strong knowledge of coverage driven verification for complex designs. Proficient in specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches. Skilled in planning verification tasks and More ❯

encouraged to mentor junior members Required Skills and Experience : Tried understanding of digital hardware design and Verilog/Systemverilog HDL Experienced in one or more of various verification methodologies - UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

be influential in bringing new verification methodologies to the table. Key skills required for this role: A solid experience in developing verification environments for RTL designs Knowledge of SystemVerilog & UVM An ability to develop new verification flows You will be involved in the execution of all verification efforts of a component or sub-system, from the planning stage to sign More ❯

and strategy. A proactive and collaborative person who actively shares feedback and who can independently define the scope of work. Proven experience of testbench design with verification frameworks like UVM/OVM. Knowledge of SystemVerilog assertion (SVA). Exposure to different programming languages, such as C, C++ and Python. You have formal verification experience. What you can expect from us More ❯

self-starting, and collaborative Ability to troubleshoot complex issues across teams and languages Experience with verification in CPU and/or ASIC environments Knowledge of SystemVerilog, Python, C++, Linux, UVM, SVA, Assembly, LLVM, GCC, Git, SGE or other DRS Familiarity with XML, XPath/XSLT We offer a competitive salary, flexible working, generous leave, private medical insurance, dental, pension (up More ❯

and recommending hardware or firmware-level fixes. Ability to lead technical discussions across architecture, firmware, software, and validation teams. "Nice To Have" Skills and Experience : Familiarity with RTL design, UVM/SystemVerilog, or hardware verification flows. Experience with trusted execution environments (TEEs) and secure monitor implementation. Understanding of secure firmware update mechanisms (rollback protection, anti-cloning). Prior work with More ❯