2 of 2 UVM Jobs in Gloucestershire

in a related subject, with 5+ years of practical experience. Skills & Experience: Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and More ❯

Knowledge of GPU/CPU architecture. Knowledge of standard bus protocols (e.g., AMBA5 CHI, AMBA4 ACE or AXI). Experience in wider verification technologies (UVM, etc.). Knowledge of a scripting language and/or C/SystemC. Understanding of functional safety standards such as ISO26262. If you are interested More ❯