4 of 4 UVM Jobs in the South West

Staff Engineers are also encouraged to mentor junior members Required Skills and Experience : Proven understanding of digital hardware design and Verilog/Systemverilog HDL Experience in SoC verification using UVM and Embedded Low-level programming experience including C/C++ and assembly language(preferably ARM) Experienced in one or more of various verification methodologies - UVM/OVM, formal, power aware More ❯

Development of Wi-Fi products, including microcontrollers and connectivity SoC/IP subsystem verification planning, test infrastructure development, functional verification. Test bench and test case generation using Verilog, SystemVerilog, UVM, C, Formal. Embedded C code or writing CPU-centric tests using C code Coverage definition, implementation and analysis Key Qualifications MSc in electrical engineering or equivalent or Bachelor with industrial … experience Strong knowledge of verification planning, assertion based and formal verification techniques, coverage based verification, UVM and C testbenches. Experience with low power verification and SoC level verification Good debugging skills Programming background in low-level and script-based languages, e.g. C, C++, Python, Perl is a plus. Fluent English language skills (written and oral) Advantageous knowledge Experience with ARM More ❯

and don't miss this opportunity to join Infineon's success story. As a Staff Verification Engineer, you will play a critical role in developing and maintaining System Verilog - UVM test benches, solving complex problems, and develop new SV UVM verification components. Your responsibilities will also include understanding and modifying Specman-e test benches, debugging failing test cases, and defining … the verification strategy and architecture of IP testbenches, ensuring test bench quality, and meeting sign-off targets. In your new role, you will: Be responsible for developing System Verilog - UVM testbench and solve potentially complex problems related to test bench development Be responsible and lead developing of new SV UVM verification components Be able to understand and modify Specman-e … A Bachelor's degree in Electrical/Electronic Engineering or equivalent degree At least 3 years of experience working in Verification, preferably at the IP level, with System Verilog - UVM; Prior knowledge in Specman-e is desirable Advanced knowledge in UVM and SVAs, System Verilog Experience with Verification platform and framework development Proven experience of ownership of IP verification including More ❯

Job Description Job Title: UVM Verification Engineer Job Type: Contract Duration: 6 months initial Location: UK/Remote Start: ASAP For our UK based client we require a Verification Engineer to join on an initial 6 month basis. The successful engineer will join an established team on a project ramp-up. Required Skills - Strong Verification background, preferably at IP/… Module level - Expertise in hardware verification languages in particular SV UVM methodology - Available to work on long-term contract (at least one year) - An interest in creating re-usable Verification IP, following guidelines for code and structure - A good listener who will gain a clear knowledge of what is required and is not afraid to ask any questions in order More ❯