6 of 6 UVM Jobs in Peterborough

microarchitecture areas, including: Instruction Fetch Instruction Decode Register Renaming Instruction Scheduling Vector Processing Load‐Store Units Knowledge of verification methodologies, including testbench development, UVM, and functional coverage. Why Join? This is an opportunity to work on technology that is helping shape the future of compute. You’ll collaborate with some ...

operating system-class subsystems alongside real-time domains A strong appreciation of the practical realities of chip implementation, including RTL design (SystemVerilog), verification methodologies (UVM, formal, emulation/FPGA), DFT, timing closure, power analysis, and physical design constraints Familiarity with scripting languages such as Bash, Python, or Tcl This role ...

emerging technology space. What you’ll be doing Lead verification strategy and execution across block, subsystem, and multi‐FPGA designs Develop scalable, high‐performance UVM environments designed to tackle complex architectures Drive verification with a strong focus on coverage, risk reduction, and system‐level behaviour Collaborate closely with the Lead … functional hardware teams Debug challenging issues spanning RTL, simulation, and hardware platforms What they’re looking for Strong hands‐on expertise in SystemVerilog and UVM Proven debugging skills across RTL, simulation, and hardware Experience owning verification planning and strategy in commercial environments Comfortable operating in fast‐moving environments with evolving ...

solutions. Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams …/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol ...

IC Resources is supporting a leading semiconductor company in recruiting a Staff/Senior Staff RTL Design Engineer to work on next-generation CPU cores. You will be involved across the full design lifecycle, delivering ...

solutions. Responsibilities Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi‐chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams …/IP‐level/SoC‐level verification Proficiency in Verilog, SystemVerilog Familiarity with industry‐standard EDA tools for simulation and debug Deep experience with UVM‐based testbenches Experience with modern programming languages like Python Knowledge of Arm AMBA protocols such as AXI, APB, and AHB Understanding of Arm CHI protocol ...