3 of 3 UVM Jobs in Renfrewshire

includes: Tools: Azure DevOps, Git, IBM DOORS, Siemens QuestaSim/ModelSim, Synopsys Synplify Pro Standards: IEC 61513, IEC 62566, IEC26262, DO 254; techniques like UVM, Formal Verification Languages: VHDL, SystemVerilog, TCL, Python We are committed to diversity, inclusion, and equal opportunity. More info at Security clearance (SC) and UK nationality More ❯

FormalPro Synopsys - Synplify Pro Standards, Frameworks and Techniques Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO-254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python The package: You'll receive a very competitive salary (£££ offered depends on level of experience More ❯

FormalPro Synopsys - Synplify Pro Standards, Frameworks and Techniques Knowledge and experience of safety standards such as IEC 61513, IEC 62566, IEC 26262, DO-254 UVM Constrained Random Testing Formal Verification Languages: VHDL, SystemVerilog, TCL, Python We're an equal opportunities employer. We're committed to developing a diverse workforce and More ❯