4 of 4 UVM Jobs in the South West

Development Verification Engineer £55,000 - £65,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you a Development Verification Engineer or similar with expertise in SystemVerilog and UVM, seeking an autonomous role where your work directly contributes to the success of a leading semiconductor company, with opportunities for career growth, ongoing development, and the potential to increase your … in the billions and a strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you will develop and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a full … time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer with SystemVerilog and UVM skills, looking to join a world-leading semiconductor company with clear progression, specialist training, and the opportunity to boost earnings through a company bonus. The Role: Take the lead in creating More ❯

and Progression) £30,000 - £35,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you an aspiring Verification Engineer looking to grow your expertise in SystemVerilog and UVM within a world-leading semiconductor company offering industry-leading training, structured progression, and the opportunity to increase your earnings through a 10% company bonus? This leading semiconductor and microcontroller provider … presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you'll work closely with experienced verification engineers to develop and maintain SystemVerilog - UVM test benches, assist in creating and integrating new verification components and debugging test cases. You'll receive hands-on training, tailored development plans, and support to enhance your technical expertise … time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This position would suit an aspiring Verification Engineer with foundational SystemVerilog and UVM knowledge, looking to join a global semiconductor leader that prioritises growth, professional development, and long-term career progression and the opportunity to boost earnings through a company bonus. The Role More ❯

automation . As an ASIC Verification Engineer , you’ll focus on the verification of WiFi SoCs , with a strong emphasis on low-power design . You’ll develop advanced UVM-based testbenches, collaborate with cross-functional teams, and help drive verification strategies for next-generation ultra-low-power wireless devices. Responsibilities Develop and implement UVM-based testbenches for ASIC verification … to ensure verification quality Qualifications Bachelor’s or Master’s in Electrical Engineering (or related field) Strong experience in ASIC verification and digital hardware design Skilled in SystemVerilog/UVM testbench development Knowledge of low-power verification techniques Familiarity with C for testbench development is a plus Experience in WiFi/wireless SoC development is desirable Excellent communication and problem … solving skills Day-to-day Collaborate with design teams to understand intent and requirements Build, maintain, and run UVM-based testbenches Perform simulations and debug issues Develop and maintain verification test plans and documentation Participate in design and code reviews What’s on offer Base salary: £60,000 – £75,000 DOE RSUs + bonus scheme Visa sponsorship and relocation support More ❯

large and ongoing investment from one of the world’s leading backers of innovative AI companies! SW Verification experience with Python, C/C++ is welcome alongside the traditional UVM based Verification. Responsibilities and Duties Verification activities within the verification team Ensuring good communication between sites Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation … programming languages to find root causes of deep and complex issues Experience of the verification process applied in CPU and/or ASIC environments System Verilog, Python, C++, Linux UVM SVA LLVM, GCC SGE or other DRMS XML and XPath/XSLT Benefits In addition to a competitive salary, you can expect flexible working, a generous annual leave policy, private More ❯