PhD in a related subject, with 5+ years of practical experience. Skills & Experience: Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC More ❯
Bristol, Gloucestershire, United Kingdom Hybrid / WFH Options
Codasip
and tracking of own work YOU SHOULD HAVE: Over 5 years recent and relevant module design experience within at least one HDL (VHDL/Verilog/SystemVerilog) Knowledge of computer systems and architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge More ❯
Fi products, including microcontrollers and connectivity SoC/IP subsystem verification planning, test infrastructure development, functional verification. Test bench and test case generation using Verilog, SystemVerilog, UVM, C, Formal. Embedded C code or writing CPU-centric tests using C. Qualifications MSc in electrical engineering or equivalent or Bachelor with industrial More ❯
Greater Bristol Area, United Kingdom Hybrid / WFH Options
IC Resources
Define verification and test plan, run regressions, reproduce, and debug functional and performance bugs. Proficiency with EDA tools (Candence, Mentor) and design languages including Verilog and systemVerilog Understanding of synthesis, static timing analysis, and netlist verifications UVM expertise Please note: You must have full UK working rights to be considered More ❯
/CXL, DDRx/LPDDRx integration verification in SoC RTL. Your key responsibilities will include writing test plans, defining test methodologies, developing SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, setting schedules, and quality checkpoints. Collaborate More ❯
of ASIC front-end design, from specification to RTL, and with a basic understanding of RTL to tape out flow. RTL Design - VHDL or Verilog Functional verification – ideally a good knowledge of System Verilog and the use of techniques such as assertions and coverage driven verification. SoC knowledge – including the More ❯
