7 of 7 Verilog Jobs in Bristol

following areas: Generating complex FPGA architectures and design implementations using VHDL, Simulink, etc., targeting Xilinx, Intel, and Microsemi devices. Ability to verify complex FPGA implementations using VHDL and System Verilog/UVM test-bench methodologies. Proficiency in FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim). Strong skills in generating low-level software (C) for FPGA test and integration More ❯

keeping designs under revision control Providing progress reports What experience you need to be the successful FPGA Engineer: At least 5 years' experience of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and More ❯

keeping designs under revision control Providing progress reports What experience you need to be the successful FPGA Engineer: At least 5 years' experience of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and More ❯

projects Required Experience Knowledge/Experience of developing/modelling/simulating software in at least one of the following areas: RF telecommunications, waveforms, OSI model, SIGINT, EW VHDL VERILOG Experience with SDR architecture Agile development methodologies. C#, C, C++, Python and Database architecture. Desirable Experience XML Networked systems JICD Restful and/or RPC API Library agnostic code development More ❯

projects Required Experience Knowledge/Experience of developing/modelling/simulating software in at least one of the following areas: RF telecommunications, waveforms, OSI model, SIGINT, EW VHDL VERILOG Experience with SDR architecture Agile development methodologies. C#, C, C++, Python and Database architecture. Desirable Experience XML Networked systems JICD Restful and/or RPC API Library agnostic code development More ❯

projects Required Experience Knowledge/Experience of developing/modelling/simulating software in at least one of the following areas: RF telecommunications, waveforms, OSI model, SIGINT, EW VHDL VERILOG Experience with SDR architecture Agile development methodologies. C#, C, C++, Python and Database architecture. Desirable Experience XML Networked systems JICD Restful and/or RPC API Library agnostic code development More ❯

Undergraduate or Graduate concentration in Electrical Engineering, Computer Science, or related areas Experience with ASIC, FPGA or other hardware/systems design and development Experience with RTL (SystemVerilog/Verilog/VHDL) Previous internship experience in hardware or low-level software engineering Experience with C, C++, or Python Passion for solving complex problems and ability to draw upon knowledge and More ❯