10 of 10 Verilog Jobs in the Thames Valley

back into the ASIC. Model algorithms and validate concepts in MATLAB/Simulink (or equivalent), ensuring functional equivalence through to gate‐level sign‐off. Own RTL development (SystemVerilog/Verilog/VHDL) including synthesis, static‐timing closure, formal and constrained‐random verification. Analyse power, performance and area (PPA); implement innovative techniques to achieve aggressive bandwidth‐per‐watt targets. Collaborate with More ❯

to candidates who hold UK citizenship or work authorization. Essential Skills 5+ years of design verification experience. Strong hands-on experience in functional verification of complex IP using System Verilog and UVM and developing reusable and scalable code. Strong scripting skills (UNIX shell scripting as well as e.g. TCL, Perl). Expert working knowledge of assertion-based verification. Hands-on More ❯

design, implementation, and verification. Strong knowledge of RTL synthesis, performance, and power analysis. In-depth understanding of digital design concepts and problem-solving capabilities. Proficient in HDL coding (VHDL, Verilog, SystemVerilog). System design knowledge, including clock domain management, reset schemes, and power management. Experience with SoC level verification (HW/SW co-verification, multi-mode simulation, gate-level simulation More ❯

metric-driven verification , including verification planning , functional coverage , code coverage , unit-level verification , and top-level verification . Expertise in testbench architecture design and hands-on experience with System Verilog , UVM , ABV , and constrained random verification . Experience with PSL , SVA , e , VMM , OVM . Familiarity with formal verification techniques such as model checking , CDC , and power-aware verification (e.g. More ❯

Engineering (CE), Electrical Engineering (EE), Computer Science (CS), or a related technical field. Prior experience in designing, coding, testing, and verifying FPGAs and/or ASICs. Proficiency in VHDL, Verilog, SystemVerilog, as well as C or C++ programming languages. Familiarity with RTL synthesis and the ability to write timing, area, and other pertinent constraints. Experience working with digital simulators and More ❯

of static & formal verification tools inc. property checking using SVA or PSL Expertise in clock/reset and low power design & verification techniques. Experience of RTL coding (VHDL/Verilog/System Verilog). Experience with Linux and Windows environments including scripting languages. Excellent presentation and communication skills in English (knowledge of other European languages would be an advantage). More ❯

ll be in your hands. As an engineer we know you'll want to know about our tech stack - and the experience you'll need there - it includes: FPGA, Verilog, C/C++, RF engineering. If you think you got what it takes to drive the development of our control systems, enable the seamless integration of classical and quantum computing More ❯

/Scan/MBIST/BSD/LBIST/Boundary Scan insertion. ATPG/TC improvements and pattern generation. Pattern simulation (Zdel/SDF) and pattern verification (VCS, NC-Verilog, NC-Sim, ModelSim). Diagnosis of ATE failures and silicon bring-up. Deep understanding of DFT architecture design and implementation. Strong problem-solving skills and ability to lead or collaborate More ❯

and CAN. Good understanding of how satellite systems work together. Experience writing test plans and running verification on avionics. Nice to have (but not essential): FPGA development (VHDL or Verilog). Python scripting for test automation. Experience working in a cleanroom or handling flight hardware. Background in GNSS, time sync, or radiation tolerance in LEO. Why this role? Flexible hybrid More ❯

and refined for a specialised edge. You’ll work on designs featuring high-speed serial I/O, PCIe interfaces, and large-scale FPGA deployments. The tooling is standard, (Verilog/SystemVerilog, Verilator, and C++,) what you build needs to be anything but. If the manufacturer thinks it's possible with their hardware, you've not gone far enough. Being More ❯