Edinburgh, Scotland, United Kingdom Hybrid / WFH Options
Leonardo
documentation for other engineers and design reviews. Experience in firmware design techniques and tools, from VHDL to place-and-route. Experience FPGA architectures such as system-on-chip (e.g. Xilinx Versal). Experience in specifying timing and area constraints for efficient FPGA place and route. Good verbal and written communication skills. Experience of working in mixed discipline teams. Degree (BSc More ❯
Edinburgh, Granton, City of Edinburgh, United Kingdom
Holt Executive
and verification methodologies Proven expertise of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA Place and Route. Ability More ❯
At least 5 years’ experience of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA Place and Route. Independent More ❯
of material for design reviews. - Development of test planning, integration and design verification. - Ensure that all firmware designs follow the company firmware process. - Experience using FPGA technologies from either Xilinx, Intel (Altera) or Microsemi (Actel) and their tools. - Degree (BSc, BEng, MEng, MSc, PhD, EngD) in Electrical & Electronic Engineering (preferable) or related science (e.g. Physics). Personal attributes and values More ❯
Edinburgh, Scotland, United Kingdom Hybrid / WFH Options
Leonardo SpA
for other engineers and design reviews. Experience in firmware design techniques and tools, from VHDL to place-and-route. Experience with FPGA architectures such as system-on-chip (e.g., Xilinx Versal). Experience in specifying timing and area constraints for efficient FPGA place and route. Good verbal and written communication skills. Experience working in mixed discipline teams. Degree (BSc, BEng More ❯
communication and leadership skills Experience of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools, including HDL Designer, ModelSim/Questa, and Precision Familiarity with Xilinx/Intel (Altera)/Microsemi (Actel) design flows and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA place and route Independent verification using VHDL More ❯
communication and leadership skills Experience of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools, including HDL Designer, ModelSim/Questa, and Precision Familiarity with Xilinx/Intel (Altera)/Microsemi (Actel) design flows and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA place and route Independent verification using VHDL More ❯
Edinburgh, Granton, City of Edinburgh, United Kingdom
Holt Executive
Experience required: Mandatory Proven expertise of developing firmware using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA Place and Route. Ability More ❯
Qualifications and Experience required: Experience of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA Place and Route. Ability More ❯