Principal Firmware Engineer, you will have experience of: Creating innovative VHDL based FPGA designs Advanced verification techniques using either VHDL or SystemVerilog/UVM Current FPGA technologies from either Xilinx, Altera or Microsemi and their tools Model Driven Engineering tools including MATLAB and Simulink High Speed Interface Design & Integration, including PCIe, DDR3, Ethernet Analysing system level documents and deriving detailed More ❯
Principal Firmware Engineer, you will have experience of: Creating innovative VHDL based FPGA designs Advanced verification techniques using either VHDL or SystemVerilog/UVM Current FPGA technologies from either Xilinx, Altera or Microsemi and their tools Model Driven Engineering tools including MATLAB and Simulink High Speed Interface Design & Integration, including PCIe, DDR3, Ethernet Analysing system level documents and deriving detailed More ❯
A minimum of 5 years of FPGA development experience using VHDL or Verilog. Proficiency with Mentor Graphics FPGA tools, including HDL Designer, ModelSim/Questa, and Precision. Experience with Xilinx, Intel (Altera), or Microsemi (Actel) FPGA design flows (ISE, Vivado, Quartus) and third-party synthesis tools. Independent verification of FPGA designs using VHDL. Proficiency in FPGA requirements capture and version More ❯
A minimum of 5 years of FPGA development experience using VHDL or Verilog. Proficiency with Mentor Graphics FPGA tools, including HDL Designer, ModelSim/Questa, and Precision. Experience with Xilinx, Intel (Altera), or Microsemi (Actel) FPGA design flows (ISE, Vivado, Quartus) and third-party synthesis tools. Independent verification of FPGA designs using VHDL. Proficiency in FPGA requirements capture and version More ❯
CPLD devices. • Using VHDL/Verilog HDL languages for FPGA design. • Implementing high speed, multi-frequency clocking architectures. • Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. • Designing for high-speed optical interfaces. • Designing for high-speed SERDES interfaces (up to 28G/56G). • Knowledge of revision control systems; CVS, Subversion, GIT or More ❯
CPLD devices. • Using VHDL/Verilog HDL languages for FPGA design. • Implementing high speed, multi-frequency clocking architectures. • Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. • Designing for high-speed optical interfaces. • Designing for high-speed SERDES interfaces (up to 28G/56G). • Knowledge of revision control systems; CVS, Subversion, GIT or More ❯
CPLD devices. • Using VHDL/Verilog HDL languages for FPGA design. • Implementing high speed, multi-frequency clocking architectures. • Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. • Designing for high-speed optical interfaces. • Designing for high-speed SERDES interfaces (up to 28G/56G). • Knowledge of revision control systems; CVS, Subversion, GIT or More ❯
CPLD devices. • Using VHDL/Verilog HDL languages for FPGA design. • Implementing high speed, multi-frequency clocking architectures. • Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. • Designing for high-speed optical interfaces. • Designing for high-speed SERDES interfaces (up to 28G/56G). • Knowledge of revision control systems; CVS, Subversion, GIT or More ❯
CPLD devices. Using VHDL/Verilog HDL languages for FPGA design. Implementing high speed, multi-frequency clocking architectures. Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. Designing for high-speed optical interfaces. Designing for high-speed SERDES interfaces (up to 28G/56G). More ❯
CPLD devices. Using VHDL/Verilog HDL languages for FPGA design. Implementing high speed, multi-frequency clocking architectures. Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. Designing for high-speed optical interfaces. Designing for high-speed SERDES interfaces (up to 28G/56G). More ❯
CPLD devices. Using VHDL/Verilog HDL languages for FPGA design. Implementing high speed, multi-frequency clocking architectures. Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. Designing for high-speed optical interfaces. Designing for high-speed SERDES interfaces (up to 28G/56G). More ❯
CPLD devices. Using VHDL/Verilog HDL languages for FPGA design. Implementing high speed, multi-frequency clocking architectures. Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets. Designing for high-speed optical interfaces. Designing for high-speed SERDES interfaces (up to 28G/56G). More ❯
the candidate must be eligible to obtain the highest level of UK security clearance . Must Have Considerable experience designing Firmware architecture using FPGA technologies and tools from either Xilinx, Intel (Altera) or Microsemi (Actel). Experience with fast interfaces such as PCIe, Ethernet, JESDC. Proficiency in advanced verification techniques such as VHDL or System Verilog/UVM. Familiarity with … Engineering, ideally specialising in FPGA/Digital techniques. Proven experience in: Creating innovative VHDL-based FPGA designs. Advanced verification techniques using VHDL or SystemVerilog/UVM. FPGA technologies from Xilinx, Altera, or Microsemi and associated tools. Model Driven Engineering tools, including MATLAB and Simulink. High-Speed Interface Design & Integration (PCIe, DDR3, Ethernet). Analysing system-level documents and deriving detailed More ❯
the candidate must be eligible to obtain the highest level of UK security clearance . Must Have Considerable experience designing Firmware architecture using FPGA technologies and tools from either Xilinx, Intel (Altera) or Microsemi (Actel). Experience with fast interfaces such as PCIe, Ethernet, JESDC. Proficiency in advanced verification techniques such as VHDL or System Verilog/UVM. Familiarity with … Engineering, ideally specialising in FPGA/Digital techniques. Proven experience in: Creating innovative VHDL-based FPGA designs. Advanced verification techniques using VHDL or SystemVerilog/UVM. FPGA technologies from Xilinx, Altera, or Microsemi and associated tools. Model Driven Engineering tools, including MATLAB and Simulink. High-Speed Interface Design & Integration (PCIe, DDR3, Ethernet). Analysing system-level documents and deriving detailed More ❯
glasgow, central scotland, united kingdom Hybrid / WFH Options
spire
of fault-tolerant systems Collaborate closely with the Electrical Engineering team to ensure optimal software-hardware integration Spin up new designs and maintain existing products with Yocto - focused on Xilinx MPSoC systems, but we also support number of other systems Key Skills: C/C++, Bash and Python Proficiency working with the Yocto framework: (for application design and base OS More ❯
