FPGA Engineer
- Location
- Oxford, England, United Kingdom
concepts, including timing closure for highly utilised designs and clock domain crossing (CDC). Toolchains: Deep experience with design and verification tools such as Xilinx Vivado, Vitis, and TCL scripting. Lab/debug skills: Familiarity with hardware debugging tools, such as JTAG debuggers, oscilloscopes, spectrum analysers, signal generators, and logic ...