1 of 1 Contract Low Latency Jobs in Cambridge

data rates Close timing in Vivado at UHD bandwidths Develop simulation testbenches and perform hardware validation Measure and optimise deterministic, sub-frame latency Required experience: Xilinx Vivado and Zynq PS/PL architecture 3G/6G/12G-SDI implementation in FPGA Frame/line buffer design and high … bandwidth DDR interfaces Real-time, low-latency video systems Broadcast video FPGA experience is essential. ...