Cambridge, Cambridgeshire, England, United Kingdom
MicroTECH Global Ltd
optimised RTL architectures Implement high-throughput, pipelined digital logic and memory interfaces Contribute to simulation, synthesis, debug, and validation of designs on Altera Agilex FPGAs and/or AMD Xilinx Versal Collaborate on architectural evaluation of latency, power, and scalability Write clean, maintainable RTL and contribute to documentation, DFT/DFM, and version control workflows Key Requirements: Minimum 7 years More ❯
communication and leadership skills Experience of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools, including HDL Designer, ModelSim/Questa, and Precision Familiarity with Xilinx/Intel (Altera)/Microsemi (Actel) design flows and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA place and route Independent verification using VHDL More ❯
communication and leadership skills Experience of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools, including HDL Designer, ModelSim/Questa, and Precision Familiarity with Xilinx/Intel (Altera)/Microsemi (Actel) design flows and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA place and route Independent verification using VHDL More ❯
communication and leadership skills Experience of developing FPGA using VHDL or Verilog Experienced with Mentor Graphics FPGA development tools, including HDL Designer, ModelSim/Questa, and Precision Familiarity with Xilinx/Intel (Altera)/Microsemi (Actel) design flows and third-party synthesis tools Experience in specifying timing and area constraints for efficient FPGA place and route Independent verification using VHDL More ❯
Cambridge, Cambridgeshire, England, United Kingdom
Avanti
the ground running and looking to start ASAP. At least twice a week in the office. Required: FPGA design with at least one of VHDL/Verilog/Systemverilog Xilinx ISE toolchain experience Telecommunications background preferred Please apply your latest CV if you have the above experience. More ❯
the ground running and looking to start ASAP. At least twice a week in the office. Required: FPGA design with at least one of VHDL/Verilog/Systemverilog Xilinx ISE toolchain experience Telecommunications background preferred Please apply your latest CV if you have the above experience. More ❯
