2 of 2 Contract UVM Jobs in Northern Ireland

with design and system teams. The focus is on building and maintaining robust verification environments and validating complex algorithms. Key Responsibilities Develop and maintain UVM, class-based verification testbenches Verify DSP/RF signal-chain blocks including FFT, FIR filters and channelizers Integrate VIP and drive constrained-random and coverage … using Git Support ASIC/SoC/FPGA verification flows Essential Skills & Experience Strong experience as a Verification Engineer/ASIC Verification Engineer Proven UVM and class-based verification expertise Solid background in DSP verification (FFT, FIR, signal processing) Python for automation and regression Experience with SoC/ASIC/ ...

complex IP and SoC designs, owning test plans, driving coverage closure, and supporting integration using industry-standard verification environments. Key Responsibilities Design and implement UVM/SystemVerilog verification environments Deliver constrained-random verification and achieve coverage sign-off Verify high-speed interfaces including Ethernet (100G) and PCIe (Gen4/Gen5 … workflows Collaborate with design, architecture, and SoC teams Essential Skills & Experience Strong experience as a Verification Engineer/Design Verification Engineer Expert knowledge of UVM and SystemVerilog Experience with Ethernet, PCIe, AMBA/AXI Proven ownership of test plans and coverage closure Python scripting and Git-based workflows Experience ...